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Commit 052aa3cc authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf vendor events: Add Bonnell V4 event file 

Add a Intel event file for perf.
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-7r1wcyb5ucqxsqzcljt3iz3b@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 19c0389b
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tools/perf/pmu-events/arch/x86/bonnell/cache.json 0 → 100644
View file @ 052aa3cc
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tools/perf/pmu-events/arch/x86/bonnell/floating-point.json 0 → 100644
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[
{
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "X87_COMP_OPS_EXE.ANY.S",
"SampleAfterValue": "2000000",
"BriefDescription": "Floating point computational micro-ops executed."
},
{
"PEBS": "2",
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "X87_COMP_OPS_EXE.ANY.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "Floating point computational micro-ops retired."
},
{
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "X87_COMP_OPS_EXE.FXCH.S",
"SampleAfterValue": "2000000",
"BriefDescription": "FXCH uops executed."
},
{
"PEBS": "2",
"EventCode": "0x10",
"Counter": "0,1",
"UMask": "0x82",
"EventName": "X87_COMP_OPS_EXE.FXCH.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "FXCH uops retired."
},
{
"EventCode": "0x11",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "FP_ASSIST.S",
"SampleAfterValue": "10000",
"BriefDescription": "Floating point assists."
},
{
"EventCode": "0x11",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "FP_ASSIST.AR",
"SampleAfterValue": "10000",
"BriefDescription": "Floating point assists for retired operations."
},
{
"EventCode": "0xB0",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_UOPS_EXEC.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD micro-ops executed (excluding stores)."
},
{
"PEBS": "2",
"EventCode": "0xB0",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "SIMD_UOPS_EXEC.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD micro-ops retired (excluding stores)."
},
{
"EventCode": "0xB1",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_SAT_UOP_EXEC.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD saturated arithmetic micro-ops executed."
},
{
"EventCode": "0xB1",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "SIMD_SAT_UOP_EXEC.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD saturated arithmetic micro-ops retired."
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed multiply micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed multiply micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed shift micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x82",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed shift micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x84",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD unpacked micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x88",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD unpacked micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed logical micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x90",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed logical micro-ops retired"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed arithmetic micro-ops executed"
},
{
"EventCode": "0xB3",
"Counter": "0,1",
"UMask": "0xa0",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD packed arithmetic micro-ops retired"
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions."
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions."
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
},
{
"EventCode": "0xC7",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "SIMD_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions."
},
{
"EventCode": "0xCD",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_ASSIST",
"SampleAfterValue": "100000",
"BriefDescription": "SIMD assists invoked."
},
{
"EventCode": "0xCE",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_INSTR_RETIRED",
"SampleAfterValue": "2000000",
"BriefDescription": "SIMD Instructions retired."
},
{
"EventCode": "0xCF",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "SIMD_SAT_INSTR_RETIRED",
"SampleAfterValue": "2000000",
"BriefDescription": "Saturated arithmetic instructions retired."
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/bonnell/frontend.json 0 → 100644
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[
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200000",
"BriefDescription": "Instruction fetches."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Icache hit"
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200000",
"BriefDescription": "Icache miss"
},
{
"EventCode": "0x86",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles during which instruction fetches are stalled."
},
{
"EventCode": "0x87",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Decode stall due to PFB empty"
},
{
"EventCode": "0x87",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "DECODE_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
"BriefDescription": "Decode stall due to IQ full"
},
{
"EventCode": "0xAA",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Non-CISC nacro instructions decoded"
},
{
"EventCode": "0xAA",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "CISC macro instructions decoded"
},
{
"EventCode": "0xAA",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "MACRO_INSTS.ALL_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "All Instructions decoded"
},
{
"EventCode": "0xA9",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "UOPS.MS_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. ",
"CounterMask": "1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/bonnell/memory.json 0 → 100644
View file @ 052aa3cc
[
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0xf",
"EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "Memory references that cross an 8-byte boundary."
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x9",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "Load splits"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0xa",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "Store splits"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x8f",
"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x89",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Load splits (At Retirement)"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x8a",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Store splits (Ar Retirement)"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x8c",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000",
"BriefDescription": "ld-op-st splits"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x97",
"EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase 1 bubble"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x91",
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase load 1 bubble"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x92",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase store 1 bubble"
},
{
"EventCode": "0x5",
"Counter": "0,1",
"UMask": "0x94",
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000",
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x81",
"EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed."
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x82",
"EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed."
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x84",
"EventName": "PREFETCH.PREFETCHT2",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed."
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x86",
"EventName": "PREFETCH.SW_L2",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x88",
"EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000",
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "PREFETCH.HW_PREFETCH",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 hardware prefetch request"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0xf",
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "Any Software prefetch"
},
{
"EventCode": "0x7",
"Counter": "0,1",
"UMask": "0x8f",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000",
"BriefDescription": "Any Software prefetch"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/bonnell/other.json 0 → 100644
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tools/perf/pmu-events/arch/x86/bonnell/pipeline.json 0 → 100644
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tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json 0 → 100644
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[
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x7",
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Memory accesses that missed the DTLB."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x5",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses due to load operations."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x9",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000",
"BriefDescription": "L0 DTLB misses due to load operations."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0x6",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses due to store operations."
},
{
"EventCode": "0x8",
"Counter": "0,1",
"UMask": "0xa",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000",
"BriefDescription": "L0 DTLB misses due to store operations"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of page-walks executed."
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Duration of page-walks in core cycles"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of D-side only page walks"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Duration of D-side only page walks"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of I-Side page walks"
},
{
"EventCode": "0xC",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Duration of I-Side page walks"
},
{
"EventCode": "0x82",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "ITLB.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB hits."
},
{
"EventCode": "0x82",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB flushes."
},
{
"PEBS": "2",
"EventCode": "0x82",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "ITLB.MISSES",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB misses."
},
{
"PEBS": "1",
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (precise event)."
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 052aa3cc
......@@ -3,3 +3,8 @@ GenuineIntel-6-56,v5,broadwellde,core
GenuineIntel-6-3D,v17,broadwell,core
GenuineIntel-6-47,v17,broadwell,core
GenuineIntel-6-4F,v10,broadwellx,core
GenuineIntel-6-1C,v4,bonnell,core
GenuineIntel-6-26,v4,bonnell,core
GenuineIntel-6-27,v4,bonnell,core
GenuineIntel-6-36,v4,bonnell,core
GenuineIntel-6-35,v4,bonnell,core
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