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Commit 060f50e3 authored by Samuel Pitoiset's avatar Samuel Pitoiset Committed by Ben Skeggs
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drm/nouveau/pm/gf100: allow to share GPC, HUB and PART domains 

Signed-off-by: default avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent f21950ea
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Showing with 34 additions and 19 deletions
drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
View file @ 060f50e3
......@@ -26,7 +26,7 @@ extern struct nvkm_oclass *nv50_pm_oclass;
extern struct nvkm_oclass *g84_pm_oclass;
extern struct nvkm_oclass *gt200_pm_oclass;
extern struct nvkm_oclass *gt215_pm_oclass;
extern struct nvkm_oclass gf100_pm_oclass;
extern struct nvkm_oclass *gf100_pm_oclass;
extern struct nvkm_oclass gk104_pm_oclass;
extern struct nvkm_oclass gk110_pm_oclass;
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View file @ 060f50e3
......@@ -90,7 +90,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->cname = "GF104";
......@@ -123,7 +123,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->cname = "GF106";
......@@ -155,7 +155,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->cname = "GF114";
......@@ -188,7 +188,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->cname = "GF116";
......@@ -220,7 +220,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->cname = "GF108";
......@@ -252,7 +252,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc8:
device->cname = "GF110";
......@@ -285,7 +285,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->cname = "GF119";
......@@ -317,7 +317,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd7:
device->cname = "GF117";
......@@ -347,7 +347,7 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
default:
nv_fatal(device, "unknown Fermi chipset\n");
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
View file @ 060f50e3
......@@ -97,11 +97,12 @@ gf100_pm_fini(struct nvkm_object *object, bool suspend)
return nvkm_pm_fini(&priv->base, suspend);
}
static int
int
gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct gf100_pm_oclass *mclass = (void *)oclass;
struct gf100_pm_priv *priv;
u32 mask;
int ret;
......@@ -113,7 +114,7 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
/* HUB */
ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
gf100_pm_hub);
mclass->doms_hub);
if (ret)
return ret;
......@@ -123,7 +124,7 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
mask &= ~nv_rd32(priv, 0x022584);
ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, gf100_pm_gpc);
0x1000, 0x200, mclass->doms_gpc);
if (ret)
return ret;
......@@ -133,7 +134,7 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, gf100_pm_part);
0x1000, 0x200, mclass->doms_part);
if (ret)
return ret;
......@@ -142,13 +143,16 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return 0;
}
struct nvkm_oclass
gf100_pm_oclass = {
.handle = NV_ENGINE(PM, 0xc0),
.ofuncs = &(struct nvkm_ofuncs) {
struct nvkm_oclass *
gf100_pm_oclass = &(struct gf100_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0xc0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_pm_ctor,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = gf100_pm_fini,
},
};
.doms_gpc = gf100_pm_gpc,
.doms_hub = gf100_pm_hub,
.doms_part = gf100_pm_part,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
View file @ 060f50e3
......@@ -2,10 +2,21 @@
#define __NVKM_PM_NVC0_H__
#include "priv.h"
struct gf100_pm_oclass {
struct nvkm_oclass base;
const struct nvkm_specdom *doms_hub;
const struct nvkm_specdom *doms_gpc;
const struct nvkm_specdom *doms_part;
};
struct gf100_pm_priv {
struct nvkm_pm base;
};
int gf100_pm_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **pobject);
struct gf100_pm_cntr {
struct nvkm_perfctr base;
};
......
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