Commit 06bfc045 authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher

drm/amdgpu: set CPU mapping of vram as cached for A+A mode

New A+A HW supports cached vram mapped to cpu.
Signed-off-by: default avatarEric Huang <jinhuieric.huang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 761d86d3
......@@ -673,7 +673,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso
mem->bus.offset += adev->gmc.aper_base;
mem->bus.is_iomem = true;
mem->bus.caching = ttm_write_combined;
if (adev->gmc.xgmi.connected_to_cpu)
mem->bus.caching = ttm_cached;
else
mem->bus.caching = ttm_write_combined;
break;
default:
return -EINVAL;
......
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