Commit 0907c8f7 authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter

drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaround

In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration

v2: SKL revision id was used for BXT, copy paste error found during
internal review (Bob Beckett).

v3: use updated macro.
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Cc: Robert Beckett <robert.beckett@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0504cffc
......@@ -1253,10 +1253,13 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
uint32_t *const batch,
uint32_t *offset)
{
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* FIXME: Replace me with WA */
wa_ctx_emit(batch, index, MI_NOOP);
/* WaDisableCtxRestoreArbitration:skl,bxt */
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* Pad to end of cacheline */
while (index % CACHELINE_DWORDS)
......@@ -1270,8 +1273,14 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
uint32_t *const batch,
uint32_t *offset)
{
struct drm_device *dev = ring->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* WaDisableCtxRestoreArbitration:skl,bxt */
if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) ||
(IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
return wa_ctx_end(wa_ctx, *offset = index, 1);
......
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