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Commit 0adc41de authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n() 

Instead of passing in the whole crtc state let's pass in just
the bits of state we need. This will help with the DRRS code
which shouldn't really be accessing the atomic state stuff directly
as it gets called outside the normal atomic flows.

v2: Fix set_m1_n1 vs. set_m2_n2 fumble for i9xx (Jani)
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-7-ville.syrjala@linux.intel.comReviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 5cd06644
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Showing with 32 additions and 25 deletions
drivers/gpu/drm/i915/display/intel_ddi.c
View file @ 0adc41de
......@@ -2498,6 +2498,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
......@@ -2510,9 +2512,9 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
intel_ddi_set_dp_msa(crtc_state, conn_state);
intel_cpu_transcoder_set_m1_n1(crtc_state,
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(crtc_state,
intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
&crtc_state->dp_m2_n2);
}
}
......
drivers/gpu/drm/i915/display/intel_display.c
View file @ 0adc41de
......@@ -118,7 +118,7 @@
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
const struct intel_link_m_n *m_n);
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
......@@ -1816,6 +1816,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
......@@ -1836,12 +1837,11 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
if (intel_crtc_has_dp_encoder(new_crtc_state)) {
if (new_crtc_state->has_pch_encoder) {
intel_pch_transcoder_set_m_n(new_crtc_state,
&new_crtc_state->dp_m_n);
intel_pch_transcoder_set_m_n(crtc, &new_crtc_state->dp_m_n);
} else {
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&new_crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(new_crtc_state,
intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
&new_crtc_state->dp_m2_n2);
}
}
......@@ -1850,7 +1850,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
intel_set_pipe_src_size(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&new_crtc_state->fdi_m_n);
ilk_set_pipeconf(new_crtc_state);
......@@ -2017,7 +2017,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
crtc_state->pixel_multiplier - 1);
if (crtc_state->has_pch_encoder)
intel_cpu_transcoder_set_m1_n1(crtc_state,
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&crtc_state->fdi_m_n);
hsw_set_frame_start_delay(crtc_state);
......@@ -2452,15 +2452,16 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
if (intel_crtc_has_dp_encoder(new_crtc_state)) {
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&new_crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(new_crtc_state,
intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
&new_crtc_state->dp_m2_n2);
}
......@@ -2508,15 +2509,16 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
if (intel_crtc_has_dp_encoder(new_crtc_state)) {
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&new_crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(new_crtc_state,
intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
&new_crtc_state->dp_m2_n2);
}
......@@ -3140,10 +3142,9 @@ static void intel_set_m_n(struct drm_i915_private *i915,
intel_de_write(i915, link_n_reg, m_n->link_n);
}
static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
const struct intel_link_m_n *m_n)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
......@@ -3165,13 +3166,12 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
}
void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
enum transcoder transcoder,
const struct intel_link_m_n *m_n)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
enum transcoder transcoder = crtc_state->cpu_transcoder;
if (DISPLAY_VER(dev_priv) >= 5)
intel_set_m_n(dev_priv, m_n,
......@@ -3183,12 +3183,11 @@ void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
void intel_cpu_transcoder_set_m2_n2(const struct intel_crtc_state *crtc_state,
void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
enum transcoder transcoder,
const struct intel_link_m_n *m_n)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder transcoder = crtc_state->cpu_transcoder;
if (!transcoder_has_m2_n2(dev_priv, transcoder))
return;
......
drivers/gpu/drm/i915/display/intel_display.h
View file @ 0adc41de
......@@ -604,9 +604,11 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);
void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
void intel_display_finish_reset(struct drm_i915_private *dev_priv);
void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
enum transcoder cpu_transcoder,
const struct intel_link_m_n *m_n);
void intel_cpu_transcoder_set_m2_n2(const struct intel_crtc_state *crtc_state,
void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
enum transcoder cpu_transcoder,
const struct intel_link_m_n *m_n);
void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
enum transcoder cpu_transcoder,
......
drivers/gpu/drm/i915/display/intel_dp_mst.c
View file @ 0adc41de
......@@ -473,6 +473,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
struct intel_digital_port *dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &dig_port->dp;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
int ret;
......@@ -523,7 +524,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(pipe_config, conn_state);
intel_cpu_transcoder_set_m1_n1(pipe_config,
intel_cpu_transcoder_set_m1_n1(crtc, pipe_config->cpu_transcoder,
&pipe_config->dp_m_n);
}
......
drivers/gpu/drm/i915/display/intel_drrs.c
View file @ 0adc41de
......@@ -115,7 +115,10 @@ static void
intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
enum drrs_refresh_rate_type refresh_type)
{
intel_cpu_transcoder_set_m1_n1(crtc_state, refresh_type == DRRS_LOW_RR ?
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder,
refresh_type == DRRS_LOW_RR ?
&crtc_state->dp_m2_n2 : &crtc_state->dp_m_n);
}
......
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