Commit 0b7515c0 authored by Samuel Pitoiset's avatar Samuel Pitoiset Committed by Ben Skeggs

drm/nouveau/pm: remove pmu signals

PDAEMON signals don't have to be exposed by the perfmon engine.
Signed-off-by: default avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: default avatarMartin Peres <martin.peres@free.fr>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 087cd0db
......@@ -12,10 +12,6 @@ struct nvkm_pm {
struct list_head domains;
u32 sequence;
/*XXX: temp for daemon backend */
u32 pwr[8];
u32 last;
};
static inline struct nvkm_pm *
......
nvkm-y += nvkm/engine/pm/base.o
nvkm-y += nvkm/engine/pm/daemon.o
nvkm-y += nvkm/engine/pm/nv40.o
nvkm-y += nvkm/engine/pm/nv50.o
nvkm-y += nvkm/engine/pm/g84.o
......
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static void
pwr_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
u32 mask = 0x00000000;
u32 ctrl = 0x00000001;
int i;
for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
mask |= 1 << (ctr->signal[i] - dom->signal);
nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
}
static void
pwr_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
struct nvkm_perfctr *ctr)
{
ctr->ctr = ppm->pwr[ctr->slot];
ctr->clk = ppm->pwr[ppm->last];
}
static void
pwr_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
{
int i;
for (i = 0; i <= ppm->last; i++) {
ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
}
}
static const struct nvkm_funcdom
pwr_perfctr_func = {
.init = pwr_perfctr_init,
.read = pwr_perfctr_read,
.next = pwr_perfctr_next,
};
const struct nvkm_specdom
gt215_pm_pwr[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nvkm_specdom
gf100_pm_pwr[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nvkm_specdom
gk104_pm_pwr[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{ 0x15, "pwr_ce2_idle" },
{}
}, &pwr_perfctr_func },
{}
};
......@@ -111,10 +111,6 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gf100_pm_pwr);
if (ret)
return ret;
/* HUB */
ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
gf100_pm_hub);
......@@ -143,7 +139,6 @@ gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
nv_engine(priv)->cclass = &nvkm_pm_cclass;
nv_engine(priv)->sclass = nvkm_pm_sclass;
priv->base.last = 7;
return 0;
}
......
......@@ -99,11 +99,6 @@ gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
/* PDAEMON */
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr);
if (ret)
return ret;
/* HUB */
ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
gk104_pm_hub);
......@@ -132,7 +127,6 @@ gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
nv_engine(priv)->cclass = &nvkm_pm_cclass;
nv_engine(priv)->sclass = nvkm_pm_sclass;
priv->base.last = 7;
return 0;
}
......
......@@ -36,10 +36,6 @@ gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret)
return ret;
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gk104_pm_pwr);
if (ret)
return ret;
nv_engine(priv)->cclass = &nvkm_pm_cclass;
nv_engine(priv)->sclass = nvkm_pm_sclass;
return 0;
......
......@@ -52,29 +52,11 @@ gt215_pm[] = {
{}
};
static int
gt215_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **object)
{
int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object);
if (ret == 0) {
struct nv40_pm_priv *priv = (void *)*object;
ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
gt215_pm_pwr);
if (ret)
return ret;
priv->base.last = 3;
}
return ret;
}
struct nvkm_oclass *
gt215_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0xa3),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gt215_pm_ctor,
.ctor = nv40_pm_ctor,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = _nvkm_pm_fini,
......
......@@ -41,10 +41,6 @@ struct nvkm_specdom {
const struct nvkm_funcdom *func;
};
extern const struct nvkm_specdom gt215_pm_pwr[];
extern const struct nvkm_specdom gf100_pm_pwr[];
extern const struct nvkm_specdom gk104_pm_pwr[];
struct nvkm_perfdom {
struct list_head head;
struct list_head list;
......
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