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Commit 0c456cfa authored by Shawn Guo's avatar Shawn Guo
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ARM: imx: rename uart and fec device tree nodes 

It has been pointed out by device tree maintainer for several times
that the generic names 'serial' and 'ethernet' should be used for
those devices per ePAPR.  Renames imx uart and fec device tree nodes
to stop them being bad examples.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent 4592a965
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Inline Side-by-side
Showing with 57 additions and 57 deletions
Documentation/devicetree/bindings/net/fsl-fec.txt
View file @ 0c456cfa
......@@ -14,7 +14,7 @@ Optional properties:
Example:
fec@83fec000 {
ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
......
Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
View file @ 0c456cfa
......@@ -11,7 +11,7 @@ Optional properties:
Example:
uart@73fbc000 {
serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
......
arch/arm/boot/dts/imx27-phytec-phycore.dts
View file @ 0c456cfa
......@@ -27,22 +27,22 @@ wdog@10002000 {
status = "okay";
};
uart@1000a000 {
serial@1000a000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart@1000b000 {
serial@1000b000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart@1000c000 {
serial@1000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
fec@1002b000 {
ethernet@1002b000 {
status = "okay";
};
......
arch/arm/boot/dts/imx27.dtsi
View file @ 0c456cfa
......@@ -59,28 +59,28 @@ wdog@10002000 {
status = "disabled";
};
uart1: uart@1000a000 {
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
status = "disabled";
};
uart2: uart@1000b000 {
uart2: serial@1000b000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000b000 0x1000>;
interrupts = <19>;
status = "disabled";
};
uart3: uart@1000c000 {
uart3: serial@1000c000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000c000 0x1000>;
interrupts = <18>;
status = "disabled";
};
uart4: uart@1000d000 {
uart4: serial@1000d000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000d000 0x1000>;
interrupts = <17>;
......@@ -183,14 +183,14 @@ cspi3: cspi@10017000 {
status = "disabled";
};
uart5: uart@1001b000 {
uart5: serial@1001b000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1001b000 0x1000>;
interrupts = <49>;
status = "disabled";
};
uart6: uart@1001c000 {
uart6: serial@1001c000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1001c000 0x1000>;
interrupts = <48>;
......@@ -206,7 +206,7 @@ i2c2: i2c@1001d000 {
status = "disabled";
};
fec: fec@1002b000 {
fec: ethernet@1002b000 {
compatible = "fsl,imx27-fec";
reg = <0x1002b000 0x4000>;
interrupts = <50>;
......
arch/arm/boot/dts/imx51-babbage.dts
View file @ 0c456cfa
......@@ -36,7 +36,7 @@ esdhc@70008000 { /* ESDHC2 */
status = "okay";
};
uart3: uart@7000c000 {
uart3: serial@7000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
......@@ -173,12 +173,12 @@ iomuxc@73fa8000 {
reg = <0x73fa8000 0x4000>;
};
uart1: uart@73fbc000 {
uart1: serial@73fbc000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart2: uart@73fc0000 {
uart2: serial@73fc0000 {
status = "okay";
};
};
......@@ -197,7 +197,7 @@ codec: sgtl5000@0a {
};
};
fec@83fec000 {
ethernet@83fec000 {
phy-mode = "mii";
status = "okay";
};
......
arch/arm/boot/dts/imx51.dtsi
View file @ 0c456cfa
......@@ -86,7 +86,7 @@ esdhc@70008000 { /* ESDHC2 */
status = "disabled";
};
uart3: uart@7000c000 {
uart3: serial@7000c000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
......@@ -171,14 +171,14 @@ wdog@73f9c000 { /* WDOG2 */
status = "disabled";
};
uart1: uart@73fbc000 {
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart2: uart@73fc0000 {
uart2: serial@73fc0000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
......@@ -235,7 +235,7 @@ i2c@83fc8000 { /* I2C1 */
status = "disabled";
};
fec@83fec000 {
ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
......
arch/arm/boot/dts/imx53-ard.dts
View file @ 0c456cfa
......@@ -40,7 +40,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
};
......
arch/arm/boot/dts/imx53-evk.dts
View file @ 0c456cfa
......@@ -71,7 +71,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
};
......@@ -95,7 +95,7 @@ codec: sgtl5000@0a {
};
};
fec@63fec000 {
ethernet@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
arch/arm/boot/dts/imx53-qsb.dts
View file @ 0c456cfa
......@@ -45,7 +45,7 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
};
......@@ -78,7 +78,7 @@ pmic: dialog@48 {
};
};
fec@63fec000 {
ethernet@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
arch/arm/boot/dts/imx53-smd.dts
View file @ 0c456cfa
......@@ -35,7 +35,7 @@ esdhc@50008000 { /* ESDHC2 */
status = "okay";
};
uart3: uart@5000c000 {
uart3: serial@5000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
......@@ -86,11 +86,11 @@ iomuxc@53fa8000 {
reg = <0x53fa8000 0x4000>;
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
status = "okay";
};
uart2: uart@53fc0000 {
uart2: serial@53fc0000 {
status = "okay";
};
};
......@@ -138,7 +138,7 @@ pmic: dialog@48 {
};
};
fec@63fec000 {
ethernet@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
......
arch/arm/boot/dts/imx53.dtsi
View file @ 0c456cfa
......@@ -88,7 +88,7 @@ esdhc@50008000 { /* ESDHC2 */
status = "disabled";
};
uart3: uart@5000c000 {
uart3: serial@5000c000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
......@@ -173,14 +173,14 @@ wdog@53f9c000 { /* WDOG2 */
status = "disabled";
};
uart1: uart@53fbc000 {
uart1: serial@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart2: uart@53fc0000 {
uart2: serial@53fc0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
......@@ -226,7 +226,7 @@ i2c@53fec000 { /* I2C3 */
status = "disabled";
};
uart4: uart@53ff0000 {
uart4: serial@53ff0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
......@@ -241,7 +241,7 @@ aips@60000000 { /* AIPS2 */
reg = <0x60000000 0x10000000>;
ranges;
uart5: uart@63f90000 {
uart5: serial@63f90000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;
......@@ -290,7 +290,7 @@ i2c@63fc8000 { /* I2C1 */
status = "disabled";
};
fec@63fec000 {
ethernet@63fec000 {
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
interrupts = <87>;
......
arch/arm/boot/dts/imx6q-arm2.dts
View file @ 0c456cfa
......@@ -23,7 +23,7 @@ memory {
soc {
aips-bus@02100000 { /* AIPS2 */
enet@02188000 {
ethernet@02188000 {
phy-mode = "rgmii";
local-mac-address = [00 04 9F 01 1B 61];
status = "okay";
......@@ -42,7 +42,7 @@ usdhc@0219c000 { /* uSDHC4 */
status = "okay";
};
uart4: uart@021f0000 {
uart4: serial@021f0000 {
status = "okay";
};
};
......
arch/arm/boot/dts/imx6q-sabrelite.dts
View file @ 0c456cfa
......@@ -23,7 +23,7 @@ memory {
soc {
aips-bus@02100000 { /* AIPS2 */
enet@02188000 {
ethernet@02188000 {
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
......@@ -43,7 +43,7 @@ usdhc@0219c000 { /* uSDHC4 */
status = "okay";
};
uart2: uart@021e8000 {
uart2: serial@021e8000 {
status = "okay";
};
......
arch/arm/boot/dts/imx6q.dtsi
View file @ 0c456cfa
......@@ -165,7 +165,7 @@ ecspi@02018000 { /* eCSPI5 */
status = "disabled";
};
uart1: uart@02020000 {
uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
......@@ -506,7 +506,7 @@ aipstz@0217c000 { /* AIPSTZ2 */
reg = <0x0217c000 0x4000>;
};
enet@02188000 {
ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
......@@ -627,28 +627,28 @@ vdoa@021e4000 {
interrupts = <0 18 0x04>;
};
uart2: uart@021e8000 {
uart2: serial@021e8000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
status = "disabled";
};
uart3: uart@021ec000 {
uart3: serial@021ec000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
status = "disabled";
};
uart4: uart@021f0000 {
uart4: serial@021f0000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
status = "disabled";
};
uart5: uart@021f4000 {
uart5: serial@021f4000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;
......
arch/arm/mach-imx/clk-imx6q.c
View file @ 0c456cfa
......@@ -392,17 +392,17 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
clk_register_clkdev(clk[twd], NULL, "smp_twd");
clk_register_clkdev(clk[usboh3], NULL, "usboh3");
clk_register_clkdev(clk[uart_serial], "per", "2020000.uart");
clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.uart");
clk_register_clkdev(clk[uart_serial], "per", "21e8000.uart");
clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.uart");
clk_register_clkdev(clk[uart_serial], "per", "21ec000.uart");
clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.uart");
clk_register_clkdev(clk[uart_serial], "per", "21f0000.uart");
clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.uart");
clk_register_clkdev(clk[uart_serial], "per", "21f4000.uart");
clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.uart");
clk_register_clkdev(clk[enet], NULL, "2188000.enet");
clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
......
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