Commit 0ce024cb authored by Sujith's avatar Sujith Committed by John W. Linville

ath9k: Clarify Interrupt mitigation

ath9k currently supports only RX interrupt
mitigation.
Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 45d5d805
...@@ -368,7 +368,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah) ...@@ -368,7 +368,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
ah->config.spurchans[i][1] = AR_NO_SPUR; ah->config.spurchans[i][1] = AR_NO_SPUR;
} }
ah->config.intr_mitigation = true; ah->config.rx_intr_mitigation = true;
/* /*
* We need this for PCI devices only (Cardbus, PCI, miniPCI) * We need this for PCI devices only (Cardbus, PCI, miniPCI)
...@@ -1160,7 +1160,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, ...@@ -1160,7 +1160,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
AR_IMR_RXORN | AR_IMR_RXORN |
AR_IMR_BCNMISC; AR_IMR_BCNMISC;
if (ah->config.intr_mitigation) if (ah->config.rx_intr_mitigation)
ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
else else
ah->mask_reg |= AR_IMR_RXOK; ah->mask_reg |= AR_IMR_RXOK;
...@@ -2091,7 +2091,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -2091,7 +2091,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
REG_WRITE(ah, AR_OBS, 8); REG_WRITE(ah, AR_OBS, 8);
if (ah->config.intr_mitigation) { if (ah->config.rx_intr_mitigation) {
REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
} }
...@@ -2751,7 +2751,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) ...@@ -2751,7 +2751,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
*masked = isr & ATH9K_INT_COMMON; *masked = isr & ATH9K_INT_COMMON;
if (ah->config.intr_mitigation) { if (ah->config.rx_intr_mitigation) {
if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
*masked |= ATH9K_INT_RX; *masked |= ATH9K_INT_RX;
} }
...@@ -2884,7 +2884,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) ...@@ -2884,7 +2884,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
} }
if (ints & ATH9K_INT_RX) { if (ints & ATH9K_INT_RX) {
mask |= AR_IMR_RXERR; mask |= AR_IMR_RXERR;
if (ah->config.intr_mitigation) if (ah->config.rx_intr_mitigation)
mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
else else
mask |= AR_IMR_RXOK | AR_IMR_RXDESC; mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
......
...@@ -212,7 +212,7 @@ struct ath9k_ops_config { ...@@ -212,7 +212,7 @@ struct ath9k_ops_config {
u32 cck_trig_low; u32 cck_trig_low;
u32 enable_ani; u32 enable_ani;
int serialize_regmode; int serialize_regmode;
bool intr_mitigation; bool rx_intr_mitigation;
#define SPUR_DISABLE 0 #define SPUR_DISABLE 0
#define SPUR_ENABLE_IOCTL 1 #define SPUR_ENABLE_IOCTL 1
#define SPUR_ENABLE_EEPROM 2 #define SPUR_ENABLE_EEPROM 2
......
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