Commit 0d0bcacc authored by David S. Miller's avatar David S. Miller

Merge branch 'mlxsw-PTP-timestamping-support'

Ido Schimmel says:

====================
mlxsw: PTP timestamping support

This is the second patchset adding PTP support in mlxsw. Next patchset
will add PTP shapers which are required to maintain accuracy under rates
lower than 40Gb/s, while subsequent patchsets will add tracepoints and
selftests.

Petr says:

This patch set introduces support for retrieving and processing hardware
timestamps for PTP packets.

The way PTP timestamping works on Spectrum-1 is that there are two queues
associated with each front panel port. When a packet is timestamped, the
timestamp is put to one of the queues: timestamps for transmitted packets
to one and for received packets to the other. Activity on these queues is
signaled through the events PTP_ING_FIFO and PTP_EGR_FIFO.

Packets themselves arrive through two traps: PTP0 and PTP1. It is possible
to configure which PTP messages should be trapped under which PTP trap. On
Spectrum systems, mlxsw will use PTP0 for event messages (which need
timestamping), and PTP1 for general messages (which do not).

There are therefore four relevant traps: receive of PTP event resp. general
message, and receive of timestamp for a transmitted resp. received PTP
packet. The obvious point where to put the new logic is a custom listener
to the mentioned traps.

Besides handling ingress traffic (be in packets or timestamps), the driver
also needs to handle timestamping of transmitted packets. One option would
be to invoke the relevant logic from mlxsw_core_ptp_transmitted(). However
on Spectrum-2, the timestamps are actually delivered through the completion
queue, and for that reason this patchset opts to invoke the logic from the
PCI code, via core and the driver, to a chip-specific operation. That way
the invocation will be done in a place where a Spectrum-2 implementation
will have an opportunity to extract the timestamp.

As indicated above, the PTP FIFO signaling happens independently from
packet delivery. A packet corresponding to any given timestamp could be
delivered sooner or later than the timestamp itself. Additionally, the
queues are only four elements deep, and it is therefore possible that the
timestamp for a delivered packet never arrives at all. Similarly a PTP
packet might be dropped due to CPU traffic pressure, and never be delivered
even if the corresponding timestamp was.

The driver thus needs to hold a cache of as-yet-unmatched SKBs and
timestamps. The first piece to arrive (be it timestamp or SKB) is put to
this cache. When the other piece arrives, the timestamp is attached to the
SKB and that is passed on. A delayed work is run at regular intervals to
prune the old unmatched entries.

As mentioned above, the mechanism for timestamp delivery changes on
Spectrum-2, where timestamps are part of completion queue elements, and all
packets are timestamped. All this bookkeeping is therefore unnecessary on
Spectrum-2. For this reason, this patchset spends some time introducing
Spectrum-1 specific artifacts such as a possibility to register a given
trap only on Spectrum-1.

Patches #1-#4 describe new registers.

Patches #5 and #6 introduce the possibility to register certain traps
only on some systems. The list of Spectrum-1 specific traps is left empty
at this point.

Patch #7 hooks into packet receive path by registering PTP traps
and appropriate handlers (that however do nothing of substance yet).

Patch #8 adds a helper to allow storing custom data to SKB->cb.

Patch #9 adds a call into the PCI completion queue handler that invokes,
via core and spectrum code, a PTP transmit handler. (Which also does not do
anything interesting yet.)

Patch #10 introduces code to invoke PTP initialization and adds data types
for the cache of unmatched entries.

Patches #11 and #12 implement the timestamping itself. In #11, the PHC
spin_locks are converted to _bh variants, because unlike normal PHC path,
which runs in process context, timestamp processing runs as soft interrupt.
Then #12 introduces the code for saving and retrieval of unmatched entries,
invokes PTP classifier to identify packets of interest, registers timestamp
FIFO events, and handles decoding and attaching timestamps to packets.

Patch #13 introduces a garbage collector for left-behind entries that have
not been matched for about a second.

In patch #14, PTP message types are configured to arrive as PTP0
(events) or PTP1 (everything else) as appropriate. At this point, the PTP
packets start arriving through the traps, but because PTP is disabled and
there is no way to enable it yet, they are always just passed to the usual
receive path right away.

Finally patches #15 and #16 add the plumbing to actually make it possible
to enable this code through SIOCSHWTSTAMP ioctl, and to advertise the
hardware timestamping capabilities through ethtool.

v2:
- Patch #12:
    - In mlxsw_sp1_ptp_fifo_event_func(), post-increment when iterating over PTP
      FIFO records.
- Patch #14:
    - Change namespace of message type enumerators from MLXSW_ to MLXSW_SP_.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6e32a74a 87ee07f8
......@@ -84,6 +84,7 @@ config MLXSW_SPECTRUM
select OBJAGG
select MLXFW
imply PTP_1588_CLOCK
select NET_PTP_CLASSIFY if PTP_1588_CLOCK
default m
---help---
This driver supports Mellanox Technologies Spectrum Ethernet
......
......@@ -1245,6 +1245,15 @@ int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
}
EXPORT_SYMBOL(mlxsw_core_skb_transmit);
void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core,
struct sk_buff *skb, u8 local_port)
{
if (mlxsw_core->driver->ptp_transmitted)
mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb,
local_port);
}
EXPORT_SYMBOL(mlxsw_core_ptp_transmitted);
static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a,
const struct mlxsw_rx_listener *rxl_b)
{
......
......@@ -48,6 +48,8 @@ bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core,
const struct mlxsw_tx_info *tx_info);
int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
const struct mlxsw_tx_info *tx_info);
void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core,
struct sk_buff *skb, u8 local_port);
struct mlxsw_rx_listener {
void (*func)(struct sk_buff *skb, u8 local_port, void *priv);
......@@ -296,6 +298,13 @@ struct mlxsw_driver {
u64 *p_linear_size);
int (*params_register)(struct mlxsw_core *mlxsw_core);
void (*params_unregister)(struct mlxsw_core *mlxsw_core);
/* Notify a driver that a timestamped packet was transmitted. Driver
* is responsible for freeing the passed-in SKB.
*/
void (*ptp_transmitted)(struct mlxsw_core *mlxsw_core,
struct sk_buff *skb, u8 local_port);
u8 txhdr_len;
const struct mlxsw_config_profile *profile;
bool res_query_enabled;
......@@ -418,4 +427,14 @@ enum mlxsw_devlink_param_id {
MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
};
struct mlxsw_skb_cb {
struct mlxsw_tx_info tx_info;
};
static inline struct mlxsw_skb_cb *mlxsw_skb_cb(struct sk_buff *skb)
{
BUILD_BUG_ON(sizeof(mlxsw_skb_cb) > sizeof(skb->cb));
return (struct mlxsw_skb_cb *) skb->cb;
}
#endif
......@@ -508,17 +508,28 @@ static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
{
struct pci_dev *pdev = mlxsw_pci->pdev;
struct mlxsw_pci_queue_elem_info *elem_info;
struct mlxsw_tx_info tx_info;
char *wqe;
struct sk_buff *skb;
int i;
spin_lock(&q->lock);
elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info;
skb = elem_info->u.sdq.skb;
wqe = elem_info->elem;
for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
dev_kfree_skb_any(skb);
if (unlikely(!tx_info.is_emad &&
skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb,
tx_info.local_port);
skb = NULL;
}
if (skb)
dev_kfree_skb_any(skb);
elem_info->u.sdq.skb = NULL;
if (q->consumer_counter++ != consumer_counter_limit)
......@@ -1548,6 +1559,7 @@ static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
err = -EAGAIN;
goto unlock;
}
mlxsw_skb_cb(skb)->tx_info = *tx_info;
elem_info->u.sdq.skb = skb;
wqe = elem_info->elem;
......@@ -1571,6 +1583,9 @@ static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
goto unmap_frags;
}
if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
/* Set unused sq entries byte count to zero. */
for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
......
......@@ -5292,6 +5292,8 @@ enum mlxsw_reg_htgt_trap_group {
MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
};
/* reg_htgt_trap_group
......@@ -9148,6 +9150,216 @@ static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
}
/* MOGCR - Monitoring Global Configuration Register
* ------------------------------------------------
*/
#define MLXSW_REG_MOGCR_ID 0x9086
#define MLXSW_REG_MOGCR_LEN 0x20
MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
/* reg_mogcr_ptp_iftc
* PTP Ingress FIFO Trap Clear
* The PTP_ING_FIFO trap provides MTPPTR with clr according
* to this value. Default 0.
* Reserved when IB switches and when SwitchX/-2, Spectrum-2
* Access: RW
*/
MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
/* reg_mogcr_ptp_eftc
* PTP Egress FIFO Trap Clear
* The PTP_EGR_FIFO trap provides MTPPTR with clr according
* to this value. Default 0.
* Reserved when IB switches and when SwitchX/-2, Spectrum-2
* Access: RW
*/
MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
/* MTPPPC - Time Precision Packet Port Configuration
* -------------------------------------------------
* This register serves for configuration of which PTP messages should be
* timestamped. This is a global configuration, despite the register name.
*
* Reserved when Spectrum-2.
*/
#define MLXSW_REG_MTPPPC_ID 0x9090
#define MLXSW_REG_MTPPPC_LEN 0x28
MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
/* reg_mtpppc_ing_timestamp_message_type
* Bitwise vector of PTP message types to timestamp at ingress.
* MessageType field as defined by IEEE 1588
* Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
* Default all 0
* Access: RW
*/
MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
/* reg_mtpppc_egr_timestamp_message_type
* Bitwise vector of PTP message types to timestamp at egress.
* MessageType field as defined by IEEE 1588
* Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
* Default all 0
* Access: RW
*/
MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
{
MLXSW_REG_ZERO(mtpppc, payload);
mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
}
/* MTPPTR - Time Precision Packet Timestamping Reading
* ---------------------------------------------------
* The MTPPTR is used for reading the per port PTP timestamp FIFO.
* There is a trap for packets which are latched to the timestamp FIFO, thus the
* SW knows which FIFO to read. Note that packets enter the FIFO before been
* trapped. The sequence number is used to synchronize the timestamp FIFO
* entries and the trapped packets.
* Reserved when Spectrum-2.
*/
#define MLXSW_REG_MTPPTR_ID 0x9091
#define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
#define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
#define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
#define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
/* reg_mtpptr_local_port
* Not supported for CPU port.
* Access: Index
*/
MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
enum mlxsw_reg_mtpptr_dir {
MLXSW_REG_MTPPTR_DIR_INGRESS,
MLXSW_REG_MTPPTR_DIR_EGRESS,
};
/* reg_mtpptr_dir
* Direction.
* Access: Index
*/
MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
/* reg_mtpptr_clr
* Clear the records.
* Access: OP
*/
MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
/* reg_mtpptr_num_rec
* Number of valid records in the response
* Range 0.. cap_ptp_timestamp_fifo
* Access: RO
*/
MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
/* reg_mtpptr_rec_message_type
* MessageType field as defined by IEEE 1588 Each bit corresponds to a value
* (e.g. Bit0: Sync, Bit1: Delay_Req)
* Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
MLXSW_REG_MTPPTR_REC_LEN, 0, false);
/* reg_mtpptr_rec_domain_number
* DomainNumber field as defined by IEEE 1588
* Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
MLXSW_REG_MTPPTR_REC_LEN, 0, false);
/* reg_mtpptr_rec_sequence_id
* SequenceId field as defined by IEEE 1588
* Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
/* reg_mtpptr_rec_timestamp_high
* Timestamp of when the PTP packet has passed through the port Units of PLL
* clock time.
* For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
* Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
/* reg_mtpptr_rec_timestamp_low
* See rec_timestamp_high.
* Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
unsigned int rec,
u8 *p_message_type,
u8 *p_domain_number,
u16 *p_sequence_id,
u64 *p_timestamp)
{
u32 timestamp_high, timestamp_low;
*p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
*p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
*p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
*p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
}
/* MTPTPT - Monitoring Precision Time Protocol Trap Register
* ---------------------------------------------------------
* This register is used for configuring under which trap to deliver PTP
* packets depending on type of the packet.
*/
#define MLXSW_REG_MTPTPT_ID 0x9092
#define MLXSW_REG_MTPTPT_LEN 0x08
MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
enum mlxsw_reg_mtptpt_trap_id {
MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
};
/* reg_mtptpt_trap_id
* Trap id.
* Access: Index
*/
MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
/* reg_mtptpt_message_type
* Bitwise vector of PTP message types to trap. This is a necessary but
* non-sufficient condition since need to enable also per port. See MTPPPC.
* Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
* Bit0: Sync, Bit1: Delay_Req)
*/
MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
static inline void mlxsw_reg_mtptptp_pack(char *payload,
enum mlxsw_reg_mtptpt_trap_id trap_id,
u16 message_type)
{
MLXSW_REG_ZERO(mtptpt, payload);
mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
mlxsw_reg_mtptpt_message_type_set(payload, message_type);
}
/* MGPIR - Management General Peripheral Information Register
* ----------------------------------------------------------
* MGPIR register allows software to query the hardware and
......@@ -10216,6 +10428,10 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(mcda),
MLXSW_REG(mgpc),
MLXSW_REG(mprs),
MLXSW_REG(mogcr),
MLXSW_REG(mtpppc),
MLXSW_REG(mtpptr),
MLXSW_REG(mtptpt),
MLXSW_REG(mgpir),
MLXSW_REG(tngcr),
MLXSW_REG(tnumt),
......
......@@ -136,6 +136,7 @@ struct mlxsw_sp_acl_tcam_ops;
struct mlxsw_sp_nve_ops;
struct mlxsw_sp_sb_vals;
struct mlxsw_sp_port_type_speed_ops;
struct mlxsw_sp_ptp_state;
struct mlxsw_sp_ptp_ops;
struct mlxsw_sp {
......@@ -157,6 +158,7 @@ struct mlxsw_sp {
struct mlxsw_sp_nve *nve;
struct notifier_block netdevice_nb;
struct mlxsw_sp_ptp_clock *clock;
struct mlxsw_sp_ptp_state *ptp_state;
struct mlxsw_sp_counter_pool *counter_pool;
struct {
......@@ -175,6 +177,8 @@ struct mlxsw_sp {
const struct mlxsw_sp_sb_vals *sb_vals;
const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
const struct mlxsw_sp_ptp_ops *ptp_ops;
const struct mlxsw_listener *listeners;
size_t listeners_count;
};
static inline struct mlxsw_sp_upper *
......@@ -262,6 +266,11 @@ struct mlxsw_sp_port {
unsigned acl_rule_count;
struct mlxsw_sp_acl_block *ing_acl_block;
struct mlxsw_sp_acl_block *eg_acl_block;
struct {
struct hwtstamp_config hwtstamp_config;
u16 ing_types;
u16 egr_types;
} ptp;
};
struct mlxsw_sp_port_type_speed_ops {
......@@ -438,6 +447,8 @@ struct mlxsw_sp_fid *mlxsw_sp_bridge_fid_get(struct mlxsw_sp *mlxsw_sp,
extern struct notifier_block mlxsw_sp_switchdev_notifier;
/* spectrum.c */
void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
u8 local_port, void *priv);
int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
bool dwrr, u8 dwrr_weight);
......
......@@ -5,11 +5,27 @@
#define _MLXSW_SPECTRUM_PTP_H
#include <linux/device.h>
#include <linux/rhashtable.h>
#include "spectrum.h"
struct mlxsw_sp;
struct mlxsw_sp_port;
struct mlxsw_sp_ptp_clock;
enum {
MLXSW_SP_PTP_MESSAGE_TYPE_SYNC,
MLXSW_SP_PTP_MESSAGE_TYPE_DELAY_REQ,
MLXSW_SP_PTP_MESSAGE_TYPE_PDELAY_REQ,
MLXSW_SP_PTP_MESSAGE_TYPE_PDELAY_RESP,
};
static inline int mlxsw_sp_ptp_get_ts_info_noptp(struct ethtool_ts_info *info)
{
info->so_timestamping = SOF_TIMESTAMPING_RX_SOFTWARE |
SOF_TIMESTAMPING_SOFTWARE;
info->phc_index = -1;
return 0;
}
#if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
struct mlxsw_sp_ptp_clock *
......@@ -17,6 +33,30 @@ mlxsw_sp1_ptp_clock_init(struct mlxsw_sp *mlxsw_sp, struct device *dev);
void mlxsw_sp1_ptp_clock_fini(struct mlxsw_sp_ptp_clock *clock);
struct mlxsw_sp_ptp_state *mlxsw_sp1_ptp_init(struct mlxsw_sp *mlxsw_sp);
void mlxsw_sp1_ptp_fini(struct mlxsw_sp_ptp_state *ptp_state);
void mlxsw_sp1_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
u8 local_port);
void mlxsw_sp1_ptp_transmitted(struct mlxsw_sp *mlxsw_sp,
struct sk_buff *skb, u8 local_port);
void mlxsw_sp1_ptp_got_timestamp(struct mlxsw_sp *mlxsw_sp, bool ingress,
u8 local_port, u8 message_type,
u8 domain_number, u16 sequence_id,
u64 timestamp);
int mlxsw_sp1_ptp_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
struct hwtstamp_config *config);
int mlxsw_sp1_ptp_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
struct hwtstamp_config *config);
int mlxsw_sp1_ptp_get_ts_info(struct mlxsw_sp *mlxsw_sp,
struct ethtool_ts_info *info);
#else
static inline struct mlxsw_sp_ptp_clock *
......@@ -29,6 +69,56 @@ static inline void mlxsw_sp1_ptp_clock_fini(struct mlxsw_sp_ptp_clock *clock)
{
}
static inline struct mlxsw_sp_ptp_state *
mlxsw_sp1_ptp_init(struct mlxsw_sp *mlxsw_sp)
{
return NULL;
}
static inline void mlxsw_sp1_ptp_fini(struct mlxsw_sp_ptp_state *ptp_state)
{
}
static inline void mlxsw_sp1_ptp_receive(struct mlxsw_sp *mlxsw_sp,
struct sk_buff *skb, u8 local_port)
{
mlxsw_sp_rx_listener_no_mark_func(skb, local_port, mlxsw_sp);
}
static inline void mlxsw_sp1_ptp_transmitted(struct mlxsw_sp *mlxsw_sp,
struct sk_buff *skb, u8 local_port)
{
dev_kfree_skb_any(skb);
}
static inline void
mlxsw_sp1_ptp_got_timestamp(struct mlxsw_sp *mlxsw_sp, bool ingress,
u8 local_port, u8 message_type,
u8 domain_number,
u16 sequence_id, u64 timestamp)
{
}
static inline int
mlxsw_sp1_ptp_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
struct hwtstamp_config *config)
{
return -EOPNOTSUPP;
}
static inline int
mlxsw_sp1_ptp_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
struct hwtstamp_config *config)
{
return -EOPNOTSUPP;
}
static inline int mlxsw_sp1_ptp_get_ts_info(struct mlxsw_sp *mlxsw_sp,
struct ethtool_ts_info *info)
{
return mlxsw_sp_ptp_get_ts_info_noptp(info);
}
#endif
static inline struct mlxsw_sp_ptp_clock *
......@@ -41,4 +131,46 @@ static inline void mlxsw_sp2_ptp_clock_fini(struct mlxsw_sp_ptp_clock *clock)
{
}
static inline struct mlxsw_sp_ptp_state *
mlxsw_sp2_ptp_init(struct mlxsw_sp *mlxsw_sp)
{
return NULL;
}
static inline void mlxsw_sp2_ptp_fini(struct mlxsw_sp_ptp_state *ptp_state)
{
}
static inline void mlxsw_sp2_ptp_receive(struct mlxsw_sp *mlxsw_sp,
struct sk_buff *skb, u8 local_port)
{
mlxsw_sp_rx_listener_no_mark_func(skb, local_port, mlxsw_sp);
}
static inline void mlxsw_sp2_ptp_transmitted(struct mlxsw_sp *mlxsw_sp,
struct sk_buff *skb, u8 local_port)
{
dev_kfree_skb_any(skb);
}
static inline int
mlxsw_sp2_ptp_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
struct hwtstamp_config *config)
{
return -EOPNOTSUPP;
}
static inline int
mlxsw_sp2_ptp_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
struct hwtstamp_config *config)
{
return -EOPNOTSUPP;
}
static inline int mlxsw_sp2_ptp_get_ts_info(struct mlxsw_sp *mlxsw_sp,
struct ethtool_ts_info *info)
{
return mlxsw_sp_ptp_get_ts_info_noptp(info);
}
#endif
......@@ -299,6 +299,8 @@ static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
u64 len;
int err;
memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
return NETDEV_TX_BUSY;
......
......@@ -17,6 +17,8 @@ enum {
MLXSW_TRAP_ID_MVRP = 0x15,
MLXSW_TRAP_ID_RPVST = 0x16,
MLXSW_TRAP_ID_DHCP = 0x19,
MLXSW_TRAP_ID_PTP0 = 0x28,
MLXSW_TRAP_ID_PTP1 = 0x29,
MLXSW_TRAP_ID_IGMP_QUERY = 0x30,
MLXSW_TRAP_ID_IGMP_V1_REPORT = 0x31,
MLXSW_TRAP_ID_IGMP_V2_REPORT = 0x32,
......@@ -76,6 +78,10 @@ enum {
enum mlxsw_event_trap_id {
/* Port Up/Down event generated by hardware */
MLXSW_TRAP_ID_PUDE = 0x8,
/* PTP Ingress FIFO has a new entry */
MLXSW_TRAP_ID_PTP_ING_FIFO = 0x2D,
/* PTP Egress FIFO has a new entry */
MLXSW_TRAP_ID_PTP_EGR_FIFO = 0x2E,
};
#endif /* _MLXSW_TRAP_H */
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