Commit 0e1610e7 authored by Neil Armstrong's avatar Neil Armstrong Committed by Kevin Hilman

arm64: dts: khadas-vim3: add SPIFC controller node

Add disabled SPIFC controller node with instruction on how to enable
it while lowering capabilities of the eMMC controller from 8bits bus
width to 4bits bus width, it's data pins 4 to 7 being shared with
the SPI NOR controller pins.
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200313090713.15147-4-narmstrong@baylibre.com
parent f12a463d
...@@ -326,6 +326,26 @@ &sd_emmc_c { ...@@ -326,6 +326,26 @@ &sd_emmc_c {
vqmmc-supply = <&emmc_1v8>; vqmmc-supply = <&emmc_1v8>;
}; };
/*
* EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
* and eMMC Data 4 to 7 pins.
* Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
* and change bus-width to 4 then spifc can be enabled.
*/
&spifc {
status = "disabled";
pinctrl-0 = <&nor_pins>;
pinctrl-names = "default";
w25q32: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128fw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
};
};
&uart_A { &uart_A {
status = "okay"; status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment