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Commit 0e75cd78 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
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[PATCH] ppc64: Update CPU features 

From: Anton Blanchard <anton@samba.org>

Update CPU features. Remove DABR feature, all cpus have it. Add MMCRA,
PMC8, SMT, COHERENT_ICACHE, LOCKLESS_TLBIE features
parent 0a8d8fbc
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Inline Side-by-side
Showing with 25 additions and 22 deletions
arch/ppc64/kernel/cputable.c
View file @ 0e75cd78
......@@ -48,7 +48,7 @@ struct cpu_spec cpu_specs[] = {
{ /* Power3 */
0xffff0000, 0x00400000, "POWER3 (630)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_DABR | CPU_FTR_IABR,
CPU_FTR_IABR | CPU_FTR_PMC8,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power3,
......@@ -57,7 +57,7 @@ struct cpu_spec cpu_specs[] = {
{ /* Power3+ */
0xffff0000, 0x00410000, "POWER3 (630+)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_DABR | CPU_FTR_IABR,
CPU_FTR_IABR | CPU_FTR_PMC8,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power3,
......@@ -66,7 +66,7 @@ struct cpu_spec cpu_specs[] = {
{ /* Northstar */
0xffff0000, 0x00330000, "RS64-II (northstar)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_DABR | CPU_FTR_IABR,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power3,
......@@ -75,7 +75,7 @@ struct cpu_spec cpu_specs[] = {
{ /* Pulsar */
0xffff0000, 0x00340000, "RS64-III (pulsar)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_DABR | CPU_FTR_IABR,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power3,
......@@ -84,7 +84,7 @@ struct cpu_spec cpu_specs[] = {
{ /* I-star */
0xffff0000, 0x00360000, "RS64-III (icestar)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_DABR | CPU_FTR_IABR,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power3,
......@@ -93,7 +93,7 @@ struct cpu_spec cpu_specs[] = {
{ /* S-star */
0xffff0000, 0x00370000, "RS64-IV (sstar)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_DABR | CPU_FTR_IABR,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power3,
......@@ -102,7 +102,7 @@ struct cpu_spec cpu_specs[] = {
{ /* Power4 */
0xffff0000, 0x00350000, "POWER4 (gp)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power4,
......@@ -111,7 +111,7 @@ struct cpu_spec cpu_specs[] = {
{ /* Power4+ */
0xffff0000, 0x00380000, "POWER4+ (gq)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power4,
......@@ -120,7 +120,8 @@ struct cpu_spec cpu_specs[] = {
{ /* PPC970 */
0xffff0000, 0x00390000, "PPC970",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
128, 128,
__setup_cpu_ppc970,
......@@ -129,7 +130,8 @@ struct cpu_spec cpu_specs[] = {
{ /* PPC970FX */
0xffff0000, 0x003c0000, "PPC970FX",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
128, 128,
__setup_cpu_ppc970,
......@@ -138,7 +140,8 @@ struct cpu_spec cpu_specs[] = {
{ /* Power5 */
0xffff0000, 0x003a0000, "POWER5 (gr)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power4,
......@@ -147,7 +150,8 @@ struct cpu_spec cpu_specs[] = {
{ /* Power5 */
0xffff0000, 0x003b0000, "POWER5 (gs)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power4,
......@@ -156,7 +160,7 @@ struct cpu_spec cpu_specs[] = {
{ /* default match */
0x00000000, 0x00000000, "POWER4 (compatible)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
CPU_FTR_PPCAS_ARCH_V2,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power4,
......
arch/ppc64/xmon/xmon.c
View file @ 0e75cd78
......@@ -452,7 +452,7 @@ insert_bpts()
}
}
if ((cur_cpu_spec->cpu_features & CPU_FTR_DABR) && dabr.enabled)
if (dabr.enabled)
set_dabr(dabr.address);
if ((cur_cpu_spec->cpu_features & CPU_FTR_IABR) && iabr.enabled)
set_iabr(iabr.address);
......@@ -465,8 +465,7 @@ remove_bpts()
struct bpt *bp;
unsigned instr;
if ((cur_cpu_spec->cpu_features & CPU_FTR_DABR))
set_dabr(0);
set_dabr(0);
if ((cur_cpu_spec->cpu_features & CPU_FTR_IABR))
set_iabr(0);
......@@ -751,10 +750,6 @@ bpt_cmds(void)
cmd = inchar();
switch (cmd) {
case 'd': /* bd - hardware data breakpoint */
if (!(cur_cpu_spec->cpu_features & CPU_FTR_DABR)) {
printf("Not implemented on this cpu\n");
break;
}
mode = 7;
cmd = inchar();
if (cmd == 'r')
......
include/asm-ppc64/cputable.h
View file @ 0e75cd78
......@@ -125,8 +125,12 @@ extern firmware_feature_t firmware_features_table[];
#define CPU_FTR_TLBIEL 0x0000000400000000
#define CPU_FTR_NOEXECUTE 0x0000000800000000
#define CPU_FTR_NODSISRALIGN 0x0000001000000000
#define CPU_FTR_DABR 0x0000002000000000
#define CPU_FTR_IABR 0x0000004000000000
#define CPU_FTR_IABR 0x0000002000000000
#define CPU_FTR_MMCRA 0x0000004000000000
#define CPU_FTR_PMC8 0x0000008000000000
#define CPU_FTR_SMT 0x0000010000000000
#define CPU_FTR_COHERENT_ICACHE 0x0000020000000000
#define CPU_FTR_LOCKLESS_TLBIE 0x0000040000000000
/* Platform firmware features */
#define FW_FTR_ 0x0000000000000001
......
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