Commit 0ec7f1ae authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman

Merge tag 'phy-fixes-5.16' of...

Merge tag 'phy-fixes-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

Vinod writes:

phy: fixes for 5.16

Fixes for:
 - kernel-doc warnings for various drivers
 - error handling fix for HiSilicon driver
 - name fix for zynqmp phy
 - property name fix in stm32 phy

* tag 'phy-fixes-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: HiSilicon: Fix copy and paste bug in error handling
  dt-bindings: phy: zynqmp-psgtr: fix USB phy name
  phy: ti: omap-usb2: Fix the kernel-doc style
  phy: qualcomm: ipq806x-usb: Fix kernel-doc style
  phy: ti: tusb1210: Fix the kernel-doc warn
  phy: qualcomm: usb-hsic: Fix the kernel-doc warn
  phy: qualcomm: qmp: Add missing struct documentation
  phy: mvebu-cp110-utmi: Fix kernel-doc warns
  phy: ti: report 2 non-kernel-doc comments
  phy: stm32: fix st,slow-hs-slew-rate with st,decrease-hs-slew-rate
parents d58071a8 f0ae8685
...@@ -29,7 +29,7 @@ properties: ...@@ -29,7 +29,7 @@ properties:
- PHY_TYPE_PCIE - PHY_TYPE_PCIE
- PHY_TYPE_SATA - PHY_TYPE_SATA
- PHY_TYPE_SGMII - PHY_TYPE_SGMII
- PHY_TYPE_USB - PHY_TYPE_USB3
- description: The PHY instance - description: The PHY instance
minimum: 0 minimum: 0
maximum: 1 # for DP, SATA or USB maximum: 1 # for DP, SATA or USB
......
...@@ -757,8 +757,8 @@ static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy, ...@@ -757,8 +757,8 @@ static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
return PTR_ERR(phy->sysctrl); return PTR_ERR(phy->sysctrl);
phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl"); phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");
if (IS_ERR(phy->sysctrl)) if (IS_ERR(phy->pmctrl))
return PTR_ERR(phy->sysctrl); return PTR_ERR(phy->pmctrl);
/* clocks */ /* clocks */
phy->phy_ref_clk = devm_clk_get(dev, "phy_ref"); phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");
......
...@@ -82,9 +82,9 @@ ...@@ -82,9 +82,9 @@
* struct mvebu_cp110_utmi - PHY driver data * struct mvebu_cp110_utmi - PHY driver data
* *
* @regs: PHY registers * @regs: PHY registers
* @syscom: Regmap with system controller registers * @syscon: Regmap with system controller registers
* @dev: device driver handle * @dev: device driver handle
* @caps: PHY capabilities * @ops: phy ops
*/ */
struct mvebu_cp110_utmi { struct mvebu_cp110_utmi {
void __iomem *regs; void __iomem *regs;
......
...@@ -127,12 +127,13 @@ struct phy_drvdata { ...@@ -127,12 +127,13 @@ struct phy_drvdata {
}; };
/** /**
* Write register and read back masked value to confirm it is written * usb_phy_write_readback() - Write register and read back masked value to
* confirm it is written
* *
* @base - QCOM DWC3 PHY base virtual address. * @phy_dwc3: QCOM DWC3 phy context
* @offset - register offset. * @offset: register offset.
* @mask - register bitmask specifying what should be updated * @mask: register bitmask specifying what should be updated
* @val - value to write. * @val: value to write.
*/ */
static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3, static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
u32 offset, u32 offset,
...@@ -171,11 +172,11 @@ static int wait_for_latch(void __iomem *addr) ...@@ -171,11 +172,11 @@ static int wait_for_latch(void __iomem *addr)
} }
/** /**
* Write SSPHY register * usb_ss_write_phycreg() - Write SSPHY register
* *
* @base - QCOM DWC3 PHY base virtual address. * @phy_dwc3: QCOM DWC3 phy context
* @addr - SSPHY address to write. * @addr: SSPHY address to write.
* @val - value to write. * @val: value to write.
*/ */
static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3, static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
u32 addr, u32 val) u32 addr, u32 val)
...@@ -209,10 +210,11 @@ static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3, ...@@ -209,10 +210,11 @@ static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
} }
/** /**
* Read SSPHY register. * usb_ss_read_phycreg() - Read SSPHY register.
* *
* @base - QCOM DWC3 PHY base virtual address. * @phy_dwc3: QCOM DWC3 phy context
* @addr - SSPHY address to read. * @addr: SSPHY address to read.
* @val: pointer in which read is store.
*/ */
static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3, static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
u32 addr, u32 *val) u32 addr, u32 *val)
......
...@@ -2973,6 +2973,9 @@ struct qmp_phy_combo_cfg { ...@@ -2973,6 +2973,9 @@ struct qmp_phy_combo_cfg {
* @qmp: QMP phy to which this lane belongs * @qmp: QMP phy to which this lane belongs
* @lane_rst: lane's reset controller * @lane_rst: lane's reset controller
* @mode: current PHY mode * @mode: current PHY mode
* @dp_aux_cfg: Display port aux config
* @dp_opts: Display port optional config
* @dp_clks: Display port clocks
*/ */
struct qmp_phy { struct qmp_phy {
struct phy *phy; struct phy *phy;
......
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/** /*
* Copyright (C) 2016 Linaro Ltd * Copyright (C) 2016 Linaro Ltd
*/ */
#include <linux/module.h> #include <linux/module.h>
......
...@@ -478,7 +478,7 @@ static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc, ...@@ -478,7 +478,7 @@ static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
if (!of_property_read_bool(np, "st,no-lsfs-fb-cap")) if (!of_property_read_bool(np, "st,no-lsfs-fb-cap"))
usbphyc_phy->tune |= LFSCAPEN; usbphyc_phy->tune |= LFSCAPEN;
if (of_property_read_bool(np, "st,slow-hs-slew-rate")) if (of_property_read_bool(np, "st,decrease-hs-slew-rate"))
usbphyc_phy->tune |= HSDRVSLEW; usbphyc_phy->tune |= HSDRVSLEW;
ret = of_property_read_u32(np, "st,tune-hs-dc-level", &val); ret = of_property_read_u32(np, "st,tune-hs-dc-level", &val);
......
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/** /*
* PCIe SERDES driver for AM654x SoC * PCIe SERDES driver for AM654x SoC
* *
* Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
......
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/** /*
* Wrapper driver for SERDES used in J721E * Wrapper driver for SERDES used in J721E
* *
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
......
...@@ -89,9 +89,9 @@ static inline void omap_usb_writel(void __iomem *addr, unsigned int offset, ...@@ -89,9 +89,9 @@ static inline void omap_usb_writel(void __iomem *addr, unsigned int offset,
} }
/** /**
* omap_usb2_set_comparator - links the comparator present in the system with * omap_usb2_set_comparator() - links the comparator present in the system with this phy
* this phy *
* @comparator - the companion phy(comparator) for this phy * @comparator: the companion phy(comparator) for this phy
* *
* The phy companion driver should call this API passing the phy_companion * The phy companion driver should call this API passing the phy_companion
* filled with set_vbus and start_srp to be used by usb phy. * filled with set_vbus and start_srp to be used by usb phy.
......
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/** /*
* tusb1210.c - TUSB1210 USB ULPI PHY driver * tusb1210.c - TUSB1210 USB ULPI PHY driver
* *
* Copyright (C) 2015 Intel Corporation * Copyright (C) 2015 Intel Corporation
......
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