Commit 0ed1a79e authored by Gaku Inami's avatar Gaku Inami Committed by Simon Horman

arm64: dts: r8a7795: Add Cortex-A57 CPU cores

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.
Signed-off-by: default avatarGaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Sigend-off-by: default avatarDirk Behme <dirk.behme@gmail.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 12e51557
......@@ -35,13 +35,31 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
/* 1 core only at this point */
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
};
a57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
};
a57_2: cpu@2 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
};
a57_3: cpu@3 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
};
};
extal_clk: extal {
......@@ -84,6 +102,7 @@ audio_clk_c: audio_clk_c {
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
......@@ -96,7 +115,7 @@ gic: interrupt-controller@0xf1010000 {
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
gpio0: gpio@e6050000 {
......@@ -214,13 +233,13 @@ gpio7: gpio@e6055800 {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
cpg: clock-controller@e6150000 {
......
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