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Commit 0ef94554 authored by Cong Yang's avatar Cong Yang Committed by Neil Armstrong
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drm/panel: himax-hx83102: Break out as separate driver 

The Starry HX83102 based mipi panel should never have been part of the boe
tv101wum-n16 driver. Discussion with Doug and Linus in V1 [1], we need a
separate driver to enable the hx83102 controller.

In hx83102 driver, add DSI commands as macros. So it can add some panels
with same control model in the future.

In the old boe-tv101wum-nl6 driver inital cmds was invoked at the end of
prepare() function , and call 0x11 and 0x29 at end of inital. For
himax-hx83102 driver, we move 0x11 and 0x29 cmds invoked at prepare()
function.

Note:0x11 is mipi_dsi_dcs_exit_sleep_mode
     0x29 is mipi_dsi_dcs_set_display_on

[1]: https://lore.kernel.org/all/CACRpkdbzYZAS0=zBQJUC4CB2wj4s1h6n6aSAZQvdMV95r3zRUw@mail.gmail.comSigned-off-by: default avatarCong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240516072039.1287065-3-yangcong5@huaqin.corp-partner.google.comSigned-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516072039.1287065-3-yangcong5@huaqin.corp-partner.google.com
parent eba54e9c
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Showing with 483 additions and 133 deletions
drivers/gpu/drm/panel/Kconfig
View file @ 0ef94554
......@@ -145,6 +145,15 @@ config DRM_PANEL_LVDS
handling of power supplies or control signals. It implements automatic
backlight handling if the panel is attached to a backlight controller.
config DRM_PANEL_HIMAX_HX83102
tristate "Himax HX83102-based panels"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
Say Y if you want to enable support for panels based on the
Himax HX83102 controller.
config DRM_PANEL_HIMAX_HX83112A
tristate "Himax HX83112A-based DSI panel"
depends on OF
......
drivers/gpu/drm/panel/Makefile
View file @ 0ef94554
......@@ -15,6 +15,7 @@ obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o
obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o
obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83102) += panel-himax-hx83102.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o
obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
......
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
View file @ 0ef94554
......@@ -1399,108 +1399,6 @@ static int starry_qfh032011_53g_init(struct boe_panel *boe)
return 0;
};
static int starry_himax83102_j02_init(struct boe_panel *boe)
{
struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi };
mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x83, 0x10, 0x21, 0x55, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x2c, 0xb5, 0xb5, 0x31, 0xf1, 0x31, 0xd7, 0x2f,
0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 0x65, 0x00, 0x88,
0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x74, 0x33);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xb2, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x12, 0x72, 0x3c,
0xa3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xf5);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x63, 0x5c,
0x63, 0x5c, 0x01, 0x9e);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0xcd);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x84);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbc, 0x1b, 0x04);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbe, 0x20);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbf, 0xfc, 0xc4);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xc0, 0x36, 0x36, 0x22, 0x11, 0x22, 0xa0, 0x61, 0x08,
0xf5, 0x03);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0xcc);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xc7, 0x80);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0xc6);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xc8, 0x97);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xc9, 0x00, 0x1e, 0x13, 0x88, 0x01);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xcb, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x33);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xcc, 0x02);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0xc4);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd0, 0x03);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0c, 0xff);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd2, 0x1f, 0x11, 0x1f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,
0x08, 0x37, 0x47, 0x34, 0x3b, 0x12, 0x12, 0x03, 0x03, 0x32,
0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32,
0x17, 0x94, 0x07, 0x94, 0x00, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1a, 0x1a, 0x1b, 0x1b,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21,
0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1a, 0x1a, 0x1b, 0x1b,
0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28,
0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd8, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xba,
0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0,
0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa,
0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe0, 0x00, 0x09, 0x14, 0x1e, 0x26, 0x48, 0x61, 0x67,
0x6c, 0x67, 0x7d, 0x7f, 0x80, 0x8b, 0x87, 0x8f, 0x98, 0xab,
0xab, 0x55, 0x5c, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1e, 0x26,
0x48, 0x61, 0x67, 0x6c, 0x67, 0x7d, 0x7f, 0x80, 0x8b, 0x87,
0x8f, 0x98, 0xab, 0xab, 0x55, 0x5c, 0x68, 0x73);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe7, 0x0e, 0x10, 0x10, 0x21, 0x2b, 0x9a, 0x02, 0x54,
0x9a, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02,
0x02, 0x10);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x01);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x01, 0xbf, 0x11);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xcb, 0x86);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd2, 0x3c, 0xfa);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd3, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
0x80, 0x0c, 0x01);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe7, 0x02, 0x00, 0x28, 0x01, 0x7e, 0x0f, 0x7e, 0x10,
0xa0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x02);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd8, 0xff, 0xff, 0xbf, 0xfe, 0xaa, 0xa0, 0xff, 0xff,
0xbf, 0xfe, 0xaa, 0xa0);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe7, 0xfe, 0x04, 0xfe, 0x04, 0xfe, 0x04, 0x03, 0x03,
0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9e,
0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x03);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0xc6);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x03, 0xff, 0xf8);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xd8, 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x2a,
0xaa, 0xa8, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xfc, 0x00, 0x00,
0x00, 0x3f, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa8,
0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0xc4);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x96);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x01);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0xc5);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x4f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xe9, 0x3f);
mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x00);
mipi_dsi_dcs_write_seq_multi(&ctx, 0x11);
if (ctx.accum_err)
return ctx.accum_err;
msleep(120);
mipi_dsi_dcs_write_seq_multi(&ctx, 0x29);
return ctx.accum_err;
};
static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
{
return container_of(panel, struct boe_panel, base);
......@@ -1859,34 +1757,6 @@ static const struct panel_desc starry_qfh032011_53g_desc = {
.lp11_before_reset = true,
};
static const struct drm_display_mode starry_himax83102_j02_default_mode = {
.clock = 162680,
.hdisplay = 1200,
.hsync_start = 1200 + 60,
.hsync_end = 1200 + 60 + 20,
.htotal = 1200 + 60 + 20 + 40,
.vdisplay = 1920,
.vsync_start = 1920 + 116,
.vsync_end = 1920 + 116 + 8,
.vtotal = 1920 + 116 + 8 + 12,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
static const struct panel_desc starry_himax83102_j02_desc = {
.modes = &starry_himax83102_j02_default_mode,
.bpc = 8,
.size = {
.width_mm = 141,
.height_mm = 226,
},
.lanes = 4,
.format = MIPI_DSI_FMT_RGB888,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM,
.init = starry_himax83102_j02_init,
.lp11_before_reset = true,
};
static int boe_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
......@@ -2062,9 +1932,6 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "starry,2081101qfh032011-53g",
.data = &starry_qfh032011_53g_desc
},
{ .compatible = "starry,himax83102-j02",
.data = &starry_himax83102_j02_desc
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, boe_of_match);
......
drivers/gpu/drm/panel/panel-himax-hx83102.c 0 → 100644
View file @ 0ef94554
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