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Commit 112525b1 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'qcom-dts-for-4.10-1' of... 

Merge tag 'qcom-dts-for-4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt

Pull "Qualcomm Device Tree Changes for v4.10 - v2" from Andy Gross:

* Add EBI2 support to MSM8660
* Add SMSC ethernet support to APQ8060
* Add support for display, pstore, iommu, and hdmi to APQ8064
* Add SDHCI node to MSM8974 Hammerhead
* Add WP8548 MangOH board support (MDM9615)

* tag 'qcom-dts-for-4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard
  ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI
  arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7
  arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes
  arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
  arm: dts: qcom: apq8064-ifc6410: Add HDMI support
  arm: dts: qcom: apq8064: Add display DT nodes
  ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node
  dt-bindings: arm: Add Sierra Wireless modules bindings
  ARM: dts: Add WP8548 based MangOH Green board DTS
  ARM: dts: Add Sierra Wireless WP8548 dtsi
  dt-bindings: qcom: Add MDM9615 bindings
  ARM: dts: Add MDM9615 dtsi
parents 2ad5c1a5 4c52ffc7
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Showing with 1658 additions and 3 deletions
Documentation/devicetree/bindings/arm/qcom.txt
View file @ 112525b1
......@@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings:
msm8916
msm8974
msm8996
mdm9615
The 'board' element must be one of the following strings:
......
Documentation/devicetree/bindings/arm/swir.txt 0 → 100644
View file @ 112525b1
Sierra Wireless Modules device tree bindings
--------------------------------------------
Supported Modules :
- WP8548 : Includes MDM9615 and PM8018 in a module
Sierra Wireless modules shall have the following properties :
Required root node property
- compatible: "swir,wp8548" for the WP8548 CF3 Module
Board compatible values:
- "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module
arch/arm/boot/dts/Makefile
View file @ 112525b1
......@@ -633,7 +633,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
qcom-msm8974-sony-xperia-honami.dtb
qcom-msm8974-sony-xperia-honami.dtb \
qcom-mdm9615-wp8548-mangoh-green.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb \
......
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
View file @ 112525b1
......@@ -51,6 +51,29 @@ vph: regulator-fixed {
regulator-boot-on;
};
/* GPIO controlled ethernet power regulator */
dragon_veth: xc622a331mrg {
compatible = "regulator-fixed";
regulator-name = "XC6222A331MR-G";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vph>;
gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&dragon_veth_gpios>;
regulator-always-on;
};
/* VDDvario fixed regulator */
dragon_vario: nds332p {
compatible = "regulator-fixed";
regulator-name = "NDS332P";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&pm8058_s3>;
};
/* This is a levelshifter for SDCC5 */
dragon_vio_txb: txb0104rgyr {
compatible = "regulator-fixed";
......@@ -167,6 +190,36 @@ rx {
bias-pull-up;
};
};
dragon_ebi2_pins: ebi2 {
/*
* Pins used by EBI2 on the Dragonboard, actually only
* CS2 is used by a real peripheral. CS0 is just
* routed to a test point.
*/
mux0 {
pins =
/* "gpio39", CS1A_N this is not good to mux */
"gpio40", /* CS2A_N */
"gpio134"; /* CS0_N testpoint TP29 */
function = "ebi2cs";
};
mux1 {
pins =
/* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
"gpio123", "gpio124", "gpio125", "gpio126",
"gpio127", "gpio128", "gpio129", "gpio130",
/* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
"gpio135", "gpio136", "gpio137", "gpio138",
"gpio139", "gpio140", "gpio141", "gpio142",
"gpio143", "gpio144", "gpio145", "gpio146",
"gpio147", "gpio148", "gpio149", "gpio150",
"gpio151", /* EBI2_OE_N */
"gpio153", /* EBI2_ADV */
"gpio157"; /* EBI2_WE_N */
function = "ebi2";
};
};
};
qcom,ssbi@500000 {
......@@ -201,6 +254,15 @@ MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE)
};
gpio@150 {
dragon_ethernet_gpios: ethernet-gpios {
pinconf {
pins = "gpio7";
function = "normal";
input-enable;
bias-disable;
power-source = <PM8058_GPIO_S3>;
};
};
dragon_bmp085_gpios: bmp085-gpios {
pinconf {
pins = "gpio16";
......@@ -238,6 +300,14 @@ pinconf {
power-source = <PM8058_GPIO_S3>;
};
};
dragon_veth_gpios: veth-gpios {
pinconf {
pins = "gpio40";
function = "normal";
bias-disable;
drive-push-pull;
};
};
};
led@48 {
......@@ -322,6 +392,55 @@ bmp085@77 {
};
};
external-bus@1a100000 {
/* The EBI2 will instantiate first, then populate its children */
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&dragon_ebi2_pins>;
/*
* An on-board SMSC LAN9221 chip for "debug ethernet",
* which is actually just an ordinary ethernet on the
* EBI2. This has a 25MHz chrystal next to it, so no
* clocking is needed.
*/
ethernet-ebi2@2,0 {
compatible = "smsc,lan9221", "smsc,lan9115";
reg = <2 0x0 0x100>;
/*
* GPIO7 has interrupt 198 on the PM8058
* The second interrupt is the PME interrupt
* for network wakeup, connected to the TLMM.
*/
interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>,
<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
vdd33a-supply = <&dragon_veth>;
vddvario-supply = <&dragon_vario>;
pinctrl-names = "default";
pinctrl-0 = <&dragon_ethernet_gpios>;
phy-mode = "mii";
reg-io-width = <2>;
smsc,force-external-phy;
/* IRQ on edge falling = active low */
smsc,irq-active-low;
smsc,irq-push-pull;
/*
* SLOW chipselect config
* Delay 9 cycles (140ns@64MHz) between SMSC
* LAN9221 Ethernet controller reads and writes
* on CS2.
*/
qcom,xmem-recovery-cycles = <0>;
qcom,xmem-write-hold-cycles = <3>;
qcom,xmem-write-delta-cycles = <31>;
qcom,xmem-read-delta-cycles = <28>;
qcom,xmem-write-wait-cycles = <9>;
qcom,xmem-read-wait-cycles = <9>;
};
};
rpm@104000 {
/*
* Set up of the PMIC RPM regulators for this board
......
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
View file @ 112525b1
......@@ -15,6 +15,20 @@ chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ramoops@88d00000{
compatible = "ramoops";
reg = <0x88d00000 0x100000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
};
};
ext_3p3v: regulator-fixed@1 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
......@@ -99,6 +113,7 @@ s7 {
l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
/* msm_otg-HSUSB_3p3 */
......@@ -133,13 +148,14 @@ l11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
bias-pull-down;
regulator-always-on;
};
/* pwm_power for backlight */
l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
bias-pull-down;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
/* camera, qdsp6 */
......@@ -184,6 +200,63 @@ lvs7 {
};
};
mdp@5100000 {
status = "okay";
ports {
port@1 {
mdp_dsi1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
dsi0: mdss_dsi@4700000 {
status = "okay";
vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/
vdd-supply = <&pm8921_l8>;
vddio-supply = <&pm8921_lvs7>;
avdd-supply = <&pm8921_l11>;
vcss-supply = <&ext_3p3v>;
panel@0 {
reg = <0>;
compatible = "jdi,lt070me05000";
vddp-supply = <&pm8921_l17>;
iovcc-supply = <&pm8921_lvs7>;
enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
ports {
port@0 {
dsi0_in: endpoint {
remote-endpoint = <&mdp_dsi1_out>;
};
};
port@1 {
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
};
};
};
dsi-phy@4700200 {
status = "okay";
vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/
};
gsbi@16200000 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C>;
......
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
View file @ 112525b1
......@@ -43,6 +43,17 @@ led@1 {
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "d";
port {
hdmi_con: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
};
soc {
pinctrl@800000 {
card_detect: card_detect {
......@@ -64,6 +75,25 @@ conf {
bias-disable;
};
};
hdmi_pinctrl: hdmi-pinctrl {
mux {
pins = "gpio70", "gpio71", "gpio72";
function = "hdmi";
};
pinconf_ddc {
pins = "gpio70", "gpio71";
bias-pull-up;
drive-strength = <2>;
};
pinconf_hpd {
pins = "gpio72";
bias-pull-down;
drive-strength = <16>;
};
};
};
rpm@108000 {
......@@ -329,5 +359,49 @@ sdcc4: sdcc@121c0000 {
mmc-pwrseq = <&sdcc4_pwrseq>;
};
};
hdmi-tx@4a00000 {
status = "okay";
core-vdda-supply = <&pm8921_hdmi_switch>;
hdmi-mux-supply = <&ext_3p3v>;
hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pinctrl>;
ports {
port@0 {
endpoint {
remote-endpoint = <&mdp_dtv_out>;
};
};
port@1 {
endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
hdmi-phy@4a00400 {
status = "okay";
core-vdda-supply = <&pm8921_hdmi_switch>;
};
mdp@5100000 {
status = "okay";
ports {
port@3 {
endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
};
arch/arm/boot/dts/qcom-apq8064.dtsi
View file @ 112525b1
......@@ -1060,6 +1060,231 @@ tcsr: syscon@1a400000 {
reg = <0x1a400000 0x100>;
};
gpu: adreno-3xx@4300000 {
compatible = "qcom,adreno-3xx";
reg = <0x04300000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 80 0>;
interrupt-names = "kgsl_3d0_irq";
clock-names =
"core_clk",
"iface_clk",
"mem_clk",
"mem_iface_clk";
clocks =
<&mmcc GFX3D_CLK>,
<&mmcc GFX3D_AHB_CLK>,
<&mmcc GFX3D_AXI_CLK>,
<&mmcc MMSS_IMEM_AHB_CLK>;
qcom,chipid = <0x03020002>;
iommus = <&gfx3d 0
&gfx3d 1
&gfx3d 2
&gfx3d 3
&gfx3d 4
&gfx3d 5
&gfx3d 6
&gfx3d 7
&gfx3d 8
&gfx3d 9
&gfx3d 10
&gfx3d 11
&gfx3d 12
&gfx3d 13
&gfx3d 14
&gfx3d 15
&gfx3d 16
&gfx3d 17
&gfx3d 18
&gfx3d 19
&gfx3d 20
&gfx3d 21
&gfx3d 22
&gfx3d 23
&gfx3d 24
&gfx3d 25
&gfx3d 26
&gfx3d 27
&gfx3d 28
&gfx3d 29
&gfx3d 30
&gfx3d 31
&gfx3d1 0
&gfx3d1 1
&gfx3d1 2
&gfx3d1 3
&gfx3d1 4
&gfx3d1 5
&gfx3d1 6
&gfx3d1 7
&gfx3d1 8
&gfx3d1 9
&gfx3d1 10
&gfx3d1 11
&gfx3d1 12
&gfx3d1 13
&gfx3d1 14
&gfx3d1 15
&gfx3d1 16
&gfx3d1 17
&gfx3d1 18
&gfx3d1 19
&gfx3d1 20
&gfx3d1 21
&gfx3d1 22
&gfx3d1 23
&gfx3d1 24
&gfx3d1 25
&gfx3d1 26
&gfx3d1 27
&gfx3d1 28
&gfx3d1 29
&gfx3d1 30
&gfx3d1 31>;
qcom,gpu-pwrlevels {
compatible = "qcom,gpu-pwrlevels";
qcom,gpu-pwrlevel@0 {
qcom,gpu-freq = <450000000>;
};
qcom,gpu-pwrlevel@1 {
qcom,gpu-freq = <27000000>;
};
};
};
mmss_sfpb: syscon@5700000 {
compatible = "syscon";
reg = <0x5700000 0x70>;
};
dsi0: mdss_dsi@4700000 {
compatible = "qcom,mdss-dsi-ctrl";
label = "MDSS DSI CTRL->0";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 82 0>;
reg = <0x04700000 0x200>;
reg-names = "dsi_ctrl";
clocks = <&mmcc DSI_M_AHB_CLK>,
<&mmcc DSI_S_AHB_CLK>,
<&mmcc AMP_AHB_CLK>,
<&mmcc DSI_CLK>,
<&mmcc DSI1_BYTE_CLK>,
<&mmcc DSI_PIXEL_CLK>,
<&mmcc DSI1_ESC_CLK>;
clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
"src_clk", "byte_clk", "pixel_clk",
"core_clk";
assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
<&mmcc DSI1_ESC_SRC>,
<&mmcc DSI_SRC>,
<&mmcc DSI_PIXEL_SRC>;
assigned-clock-parents = <&dsi0_phy 0>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi0_phy 1>;
syscon-sfpb = <&mmss_sfpb>;
phys = <&dsi0_phy>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi0_phy: dsi-phy@4700200 {
compatible = "qcom,dsi-phy-28nm-8960";
#clock-cells = <1>;
reg = <0x04700200 0x100>,
<0x04700300 0x200>,
<0x04700500 0x5c>;
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
clock-names = "iface_clk";
clocks = <&mmcc DSI_M_AHB_CLK>;
};
mdp_port0: iommu@7500000 {
compatible = "qcom,apq8064-iommu";
#iommu-cells = <1>;
clock-names =
"smmu_pclk",
"iommu_clk";
clocks =
<&mmcc SMMU_AHB_CLK>,
<&mmcc MDP_AXI_CLK>;
reg = <0x07500000 0x100000>;
interrupts =
<GIC_SPI 63 0>,
<GIC_SPI 64 0>;
qcom,ncb = <2>;
};
mdp_port1: iommu@7600000 {
compatible = "qcom,apq8064-iommu";
#iommu-cells = <1>;
clock-names =
"smmu_pclk",
"iommu_clk";
clocks =
<&mmcc SMMU_AHB_CLK>,
<&mmcc MDP_AXI_CLK>;
reg = <0x07600000 0x100000>;
interrupts =
<GIC_SPI 61 0>,
<GIC_SPI 62 0>;
qcom,ncb = <2>;
};
gfx3d: iommu@7c00000 {
compatible = "qcom,apq8064-iommu";
#iommu-cells = <1>;
clock-names =
"smmu_pclk",
"iommu_clk";
clocks =
<&mmcc SMMU_AHB_CLK>,
<&mmcc GFX3D_AXI_CLK>;
reg = <0x07c00000 0x100000>;
interrupts =
<GIC_SPI 69 0>,
<GIC_SPI 70 0>;
qcom,ncb = <3>;
};
gfx3d1: iommu@7d00000 {
compatible = "qcom,apq8064-iommu";
#iommu-cells = <1>;
clock-names =
"smmu_pclk",
"iommu_clk";
clocks =
<&mmcc SMMU_AHB_CLK>,
<&mmcc GFX3D_AXI_CLK>;
reg = <0x07d00000 0x100000>;
interrupts =
<GIC_SPI 210 0>,
<GIC_SPI 211 0>;
qcom,ncb = <3>;
};
pcie: pci@1b500000 {
compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
reg = <0x1b500000 0x1000
......@@ -1095,6 +1320,102 @@ pcie: pci@1b500000 {
reset-names = "axi", "ahb", "por", "pci", "phy";
status = "disabled";
};
hdmi: hdmi-tx@4a00000 {
compatible = "qcom,hdmi-tx-8960";
reg = <0x04a00000 0x2f0>;
reg-names = "core_physical";
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc HDMI_APP_CLK>,
<&mmcc HDMI_M_AHB_CLK>,
<&mmcc HDMI_S_AHB_CLK>;
clock-names = "core_clk",
"master_iface_clk",
"slave_iface_clk";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
};
};
port@1 {
reg = <1>;
hdmi_out: endpoint {
};
};
};
};
hdmi_phy: hdmi-phy@4a00400 {
compatible = "qcom,hdmi-phy-8960";
reg = <0x4a00400 0x60>,
<0x4a00500 0x100>;
reg-names = "hdmi_phy",
"hdmi_pll";
clocks = <&mmcc HDMI_S_AHB_CLK>;
clock-names = "slave_iface_clk";
};
mdp: mdp@5100000 {
compatible = "qcom,mdp4";
reg = <0x05100000 0xf0000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc MDP_CLK>,
<&mmcc MDP_AHB_CLK>,
<&mmcc MDP_AXI_CLK>,
<&mmcc MDP_LUT_CLK>,
<&mmcc HDMI_TV_CLK>,
<&mmcc MDP_TV_CLK>;
clock-names = "core_clk",
"iface_clk",
"bus_clk",
"lut_clk",
"hdmi_clk",
"tv_clk";
iommus = <&mdp_port0 0
&mdp_port0 2
&mdp_port1 0
&mdp_port1 2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp_lvds_out: endpoint {
};
};
port@1 {
reg = <1>;
mdp_dsi1_out: endpoint {
};
};
port@2 {
reg = <2>;
mdp_dsi2_out: endpoint {
};
};
port@3 {
reg = <3>;
mdp_dtv_out: endpoint {
};
};
};
};
};
};
#include "qcom-apq8064-pins.dtsi"
arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts 0 → 100644
View file @ 112525b1
/*
* Device Tree Source for mangOH Green Board with WP8548 Module
*
* Copyright (C) 2016 BayLibre, SAS.
* Author : Neil Armstrong <narmstrong@baylibre.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include "qcom-mdm9615-wp8548.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "MangOH Green with WP8548 Module";
compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615";
aliases {
spi0 = &gsbi3_spi;
serial0 = &gsbi4_serial;
serial1 = &gsbi5_serial;
i2c0 = &gsbi5_i2c;
mmc0 = &sdcc1;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&msmgpio {
/* MangOH GPIO Mapping :
* - 2 : GPIOEXP_INT2
* - 7 : IOT1_GPIO2
* - 8 : IOT0_GPIO4
* - 13: IOT0_GPIO3
* - 21: IOT1_GPIO4
* - 22: IOT2_GPIO1
* - 23: IOT2_GPIO2
* - 24: IOT2_GPIO3
* - 25: IOT1_GPIO1
* - 32: IOT1_GPIO3
* - 33: IOT0_GPIO2
* - 42: IOT0_GPIO1 and SD Card Detect
*/
gpioext1_pins: gpioext1_pins {
pins {
pins = "gpio2";
function = "gpio";
input-enable;
bias-disable;
};
};
sdc_cd_pins: sdc_cd_pins {
pins {
pins = "gpio42";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&gsbi3_spi {
spi@0 {
compatible = "swir,mangoh-iotport-spi", "spidev";
spi-max-frequency = <24000000>;
reg = <0>;
};
};
&gsbi5_i2c {
mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c_iot0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_iot1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_iot2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
usbhub: hub@8 {
compatible = "smsc,usb3503a";
reg = <0x8>;
connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>;
intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
gpioext0: gpio@3e {
/* GPIO Expander 0 Mapping :
* - 0: ARDUINO_RESET_Level shift
* - 1: BattChrgr_PG_N
* - 2: BattGauge_GPIO
* - 3: LED_ON (out active high)
* - 4: ATmega_reset_GPIO
* - 5: X
* - 6: PCM_ANALOG_SELECT (out active high)
* - 7: X
* - 8: Board_rev_res1 (in)
* - 9: Board_rev_res2 (in)
* - 10: UART_EXP1_ENn (out active low / pull-down)
* - 11: UART_EXP1_IN (out pull-down)
* - 12: UART_EXP2_IN (out pull-down)
* - 13: SDIO_SEL (out pull-down)
* - 14: SPI_EXP1_ENn (out active low / pull-down)
* - 15: SPI_EXP1_IN (out pull-down)
*/
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "semtech,sx1509q";
reg = <0x3e>;
interrupt-parent = <&gpioext1>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
probe-reset;
gpio-controller;
interrupt-controller;
};
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
gpioext1: gpio@3f {
/* GPIO Expander 1 Mapping :
* - 0: GPIOEXP_INT1
* - 1: Battery detect
* - 2: GPIO_SCF3_RESET
* - 3: LED_CARD_DETECT_IOT0 (in)
* - 4: LED_CARD_DETECT_IOT1 (in)
* - 5: LED_CARD_DETECT_IOT2 (in)
* - 6: UIM2_PWM_SELECT
* - 7: UIM2_M2_S_SELECT
* - 8: TP900
* - 9: SENSOR_INT1 (in)
* - 10: SENSOR_INT2 (in)
* - 11: CARD_DETECT_IOT0 (in pull-up)
* - 12: CARD_DETECT_IOT2 (in pull-up)
* - 13: CARD_DETECT_IOT1 (in pull-up)
* - 14: GPIOEXP_INT3 (in active low / pull-up)
* - 15: BattChrgr_INT_N
*/
pinctrl-0 = <&gpioext1_pins>;
pinctrl-names = "default";
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "semtech,sx1509q";
reg = <0x3f>;
interrupt-parent = <&msmgpio>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
probe-reset;
gpio-controller;
interrupt-controller;
};
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
gpioext2: gpio@70 {
/* GPIO Expander 2 Mapping :
* - 0: USB_HUB_INTn
* - 1: HUB_CONNECT
* - 2: GPIO_IOT2_RESET (out active low / pull-up)
* - 3: GPIO_IOT1_RESET (out active low / pull-up)
* - 4: GPIO_IOT0_RESET (out active low / pull-up)
* - 5: TP901
* - 6: TP902
* - 7: TP903
* - 8: UART_EXP2_ENn (out active low / pull-down)
* - 9: PCM_EXP1_ENn (out active low)
* - 10: PCM_EXP1_SEL (out)
* - 11: ARD_FTDI
* - 12: TP904
* - 13: TP905
* - 14: TP906
* - 15: RS232_Enable (out active high / pull-up)
*/
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "semtech,sx1509q";
reg = <0x70>;
interrupt-parent = <&gpioext1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
probe-reset;
gpio-controller;
interrupt-controller;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&sdcc1 {
pinctrl-0 = <&sdc_cd_pins>;
pinctrl-names = "default";
disable-wp;
cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */
};
arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi 0 → 100644
View file @ 112525b1
/*
* Device Tree Source for Sierra Wireless WP8548 Module
*
* Copyright (C) 2016 BayLibre, SAS.
* Author : Neil Armstrong <narmstrong@baylibre.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "qcom-mdm9615.dtsi"
/ {
model = "Sierra Wireless WP8548 Module";
compatible = "swir,wp8548", "qcom,mdm9615";
memory {
reg = <0x48000000 0x7F00000>;
};
};
&msmgpio {
pinctrl-0 = <&reset_out_pins>;
pinctrl-names = "default";
gsbi3_pins: gsbi3_pins {
mux {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "gsbi3";
drive-strength = <8>;
bias-disable;
};
};
gsbi4_pins: gsbi4_pins {
mux {
pins = "gpio12", "gpio13", "gpio14", "gpio15";
function = "gsbi4";
drive-strength = <8>;
bias-disable;
};
};
gsbi5_i2c_pins: gsbi5_i2c_pins {
pin16 {
pins = "gpio16";
function = "gsbi5_i2c";
drive-strength = <8>;
bias-disable;
};
pin17 {
pins = "gpio17";
function = "gsbi5_i2c";
drive-strength = <2>;
bias-disable;
};
};
gsbi5_uart_pins: gsbi5_uart_pins {
mux {
pins = "gpio18", "gpio19";
function = "gsbi5_uart";
drive-strength = <8>;
bias-disable;
};
};
reset_out_pins: reset_out_pins {
pins {
pins = "gpio66";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
output-high;
};
};
};
&pmicgpio {
usb_vbus_5v_pins: usb_vbus_5v_pins {
pins = "gpio4";
function = "normal";
output-high;
bias-disable;
qcom,drive-strength = <1>;
power-source = <2>;
};
};
&gsbi3 {
status = "ok";
qcom,mode = <GSBI_PROT_SPI>;
};
&gsbi3_spi {
status = "ok";
pinctrl-0 = <&gsbi3_pins>;
pinctrl-names = "default";
assigned-clocks = <&gcc GSBI3_QUP_CLK>;
assigned-clock-rates = <24000000>;
};
&gsbi4 {
status = "ok";
qcom,mode = <GSBI_PROT_UART_W_FC>;
};
&gsbi4_serial {
status = "ok";
pinctrl-0 = <&gsbi4_pins>;
pinctrl-names = "default";
};
&gsbi5 {
status = "ok";
qcom,mode = <GSBI_PROT_I2C_UART>;
};
&gsbi5_i2c {
status = "ok";
clock-frequency = <200000>;
pinctrl-0 = <&gsbi5_i2c_pins>;
pinctrl-names = "default";
};
&gsbi5_serial {
status = "ok";
pinctrl-0 = <&gsbi5_uart_pins>;
pinctrl-names = "default";
};
&sdcc1 {
status = "ok";
};
arch/arm/boot/dts/qcom-mdm9615.dtsi 0 → 100644
View file @ 112525b1
This diff is collapsed.
arch/arm/boot/dts/qcom-msm8660.dtsi
View file @ 112525b1
......@@ -141,6 +141,23 @@ gsbi12_i2c: i2c@19c80000 {
};
};
external-bus@1a100000 {
compatible = "qcom,msm8660-ebi2";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
reg-names = "ebi2", "xmem";
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
clock-names = "ebi2x", "ebi2";
status = "disabled";
};
qcom,ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
......
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
View file @ 112525b1
......@@ -224,6 +224,35 @@ serial@f991d000 {
status = "ok";
};
pinctrl@fd510000 {
sdhc1_pin_a: sdhc1-pin-active {
clk {
pins = "sdc1_clk";
drive-strength = <16>;
bias-disable;
};
cmd-data {
pins = "sdc1_cmd", "sdc1_data";
drive-strength = <10>;
bias-pull-up;
};
};
};
sdhci@f9824900 {
status = "ok";
vmmc-supply = <&pm8941_l20>;
vqmmc-supply = <&pm8941_s3>;
bus-width = <8>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdhc1_pin_a>;
};
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
......
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