perf cacheline: Move cacheline related routines to separate files

To disentangle util/sort.h a bit more.

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Link: https://lkml.kernel.org/n/tip-6kbf2cauas06rbqp15pyter5@git.kernel.orgSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent aeb00b1a
......@@ -26,6 +26,7 @@
#include "hist.h"
#include "sort.h"
#include "tool.h"
#include "cacheline.h"
#include "data.h"
#include "event.h"
#include "evlist.h"
......
perf-y += annotate.o
perf-y += block-range.o
perf-y += build-id.o
perf-y += cacheline.o
perf-y += config.o
perf-y += ctype.o
perf-y += db-export.o
......
// SPDX-License-Identifier: GPL-2.0
#include "cacheline.h"
#include "../perf.h"
#include <unistd.h>
#ifdef _SC_LEVEL1_DCACHE_LINESIZE
#define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE)
#else
#include <api/fs/fs.h>
#include "debug.h"
static void cache_line_size(int *cacheline_sizep)
{
if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep))
pr_debug("cannot determine cache line size");
}
#endif
int cacheline_size(void)
{
static int size;
if (!size)
cache_line_size(&size);
return size;
}
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef PERF_CACHELINE_H
#define PERF_CACHELINE_H
#include <linux/compiler.h>
int __pure cacheline_size(void);
static inline u64 cl_address(u64 address)
{
/* return the cacheline of the address */
return (address & ~(cacheline_size() - 1));
}
static inline u64 cl_offset(u64 address)
{
/* return the cacheline of the address */
return (address & (cacheline_size() - 1));
}
#endif // PERF_CACHELINE_H
......@@ -6,6 +6,7 @@
#include <linux/time64.h>
#include "sort.h"
#include "hist.h"
#include "cacheline.h"
#include "comm.h"
#include "map.h"
#include "symbol.h"
......
......@@ -204,18 +204,6 @@ static inline float hist_entry__get_percent_limit(struct hist_entry *he)
return period * 100.0 / total_period;
}
static inline u64 cl_address(u64 address)
{
/* return the cacheline of the address */
return (address & ~(cacheline_size() - 1));
}
static inline u64 cl_offset(u64 address)
{
/* return the cacheline of the address */
return (address & (cacheline_size() - 1));
}
enum sort_mode {
SORT_MODE__NORMAL,
SORT_MODE__BRANCH,
......
......@@ -43,26 +43,6 @@ void perf_set_multithreaded(void)
unsigned int page_size;
#ifdef _SC_LEVEL1_DCACHE_LINESIZE
#define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE)
#else
static void cache_line_size(int *cacheline_sizep)
{
if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep))
pr_debug("cannot determine cache line size");
}
#endif
int cacheline_size(void)
{
static int size;
if (!size)
cache_line_size(&size);
return size;
}
int sysctl_perf_event_max_stack = PERF_MAX_STACK_DEPTH;
int sysctl_perf_event_max_contexts_per_stack = PERF_MAX_CONTEXTS_PER_STACK;
......
......@@ -34,7 +34,6 @@ int copyfile_offset(int ifd, loff_t off_in, int ofd, loff_t off_out, u64 size);
size_t hex_width(u64 v);
extern unsigned int page_size;
int __pure cacheline_size(void);
int sysctl__max_stack(void);
......
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