Commit 13cde090 authored by Xiubo Li's avatar Xiubo Li Committed by Mark Brown

ASoC: fsl-sai: fix Freescale SAI DAI format setting.

o Fix some bugs of fsl_sai_set_dai_fmt_tr().
o Add SND_SOC_DAIFMT_LEFT_J support.
o Add SND_SOC_DAIFMT_CBS_CFM support.
o Add SND_SOC_DAIFMT_CBM_CFS support.
o And SND_SOC_DAIFMT_RIGHT_J need to be done in the future.
Signed-off-by: default avatarXiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent 7d150c60
...@@ -105,35 +105,47 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, ...@@ -105,35 +105,47 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
else else
val_cr4 |= FSL_SAI_CR4_MF; val_cr4 |= FSL_SAI_CR4_MF;
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S: case SND_SOC_DAIFMT_I2S:
val_cr4 |= FSL_SAI_CR4_FSE; /* Data on rising edge of bclk, frame low, 1clk before data */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
break;
case SND_SOC_DAIFMT_LEFT_J:
/* Data on rising edge of bclk, frame high, 0clk before data */
val_cr2 &= ~FSL_SAI_CR2_BCP;
val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
break; break;
case SND_SOC_DAIFMT_RIGHT_J:
/* To be done */
default: default:
return -EINVAL; return -EINVAL;
} }
/* DAI clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) { switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF: case SND_SOC_DAIFMT_IB_IF:
val_cr4 |= FSL_SAI_CR4_FSP; /* Invert both clocks */
val_cr2 &= ~FSL_SAI_CR2_BCP; val_cr2 ^= FSL_SAI_CR2_BCP;
val_cr4 ^= FSL_SAI_CR4_FSP;
break; break;
case SND_SOC_DAIFMT_IB_NF: case SND_SOC_DAIFMT_IB_NF:
val_cr4 &= ~FSL_SAI_CR4_FSP; /* Invert bit clock */
val_cr2 &= ~FSL_SAI_CR2_BCP; val_cr2 ^= FSL_SAI_CR2_BCP;
break; break;
case SND_SOC_DAIFMT_NB_IF: case SND_SOC_DAIFMT_NB_IF:
val_cr4 |= FSL_SAI_CR4_FSP; /* Invert frame clock */
val_cr2 |= FSL_SAI_CR2_BCP; val_cr4 ^= FSL_SAI_CR4_FSP;
break; break;
case SND_SOC_DAIFMT_NB_NF: case SND_SOC_DAIFMT_NB_NF:
val_cr4 &= ~FSL_SAI_CR4_FSP; /* Nothing to do for both normal cases */
val_cr2 |= FSL_SAI_CR2_BCP;
break; break;
default: default:
return -EINVAL; return -EINVAL;
} }
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS: case SND_SOC_DAIFMT_CBS_CFS:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR; val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
...@@ -143,6 +155,14 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, ...@@ -143,6 +155,14 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR; val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR; val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
break; break;
case SND_SOC_DAIFMT_CBS_CFM:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
break;
default: default:
return -EINVAL; return -EINVAL;
} }
......
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