arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi

To simplify the representation of differences betweem the G12A and G12B
SoCs, move the common nodes into a meson-g12-common.dtsi file and
express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi.

This separation will help for DVFS and future Amlogic SM1 Family support.

The sd_emmc_a quirk is added in the g12a/g12b since since it's already
known the sd_emmc_a controller is fixed in the next SM1 SoC family.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

arch/arm64/boot/dts/amlogic/meson-g12b.dtsi

@@ -4,12 +4,15 @@
  * Author: Neil Armstrong <narmstrong@baylibre.com>
  */
 
-#include "meson-g12a.dtsi"
+#include "meson-g12-common.dtsi"
 
 / {
 	compatible = "amlogic,g12b";
 
 	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
 		cpu-map {
 			cluster0 {
 				core0 {
@@ -40,8 +43,21 @@ core3 {
 			};
 		};
 
-		/delete-node/ cpu@2;
-		/delete-node/ cpu@3;
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
 
 		cpu100: cpu@100 {
 			device_type = "cpu";
@@ -74,9 +90,17 @@ cpu103: cpu@103 {
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+		};
 	};
 };
 
 &clkc {
 	compatible = "amlogic,g12b-clkc";
 };
+
+&sd_emmc_a {
+	amlogic,dram-access-quirk;
+};