Commit 14bd8572 authored by Weidong Wang's avatar Weidong Wang Committed by Mark Brown

ASoC: codecs: Aw88395 chip register file, data type file and Kconfig Makefile

The Awinic AW88395 is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost convert
Signed-off-by: default avatarNick Li <liweilei@awinic.com>
Signed-off-by: default avatarBruce zhao <zhaolei@awinic.com>
Signed-off-by: default avatarWeidong Wang <wangweidong.a@awinic.com>
Link: https://lore.kernel.org/r/20230113055301.189541-5-wangweidong.a@awinic.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 06d2fe9c
......@@ -54,6 +54,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_ALC5623
imply SND_SOC_ALC5632
imply SND_SOC_AW8738
imply SND_SOC_AW88395
imply SND_SOC_BT_SCO
imply SND_SOC_BD28623
imply SND_SOC_CQ0093VC
......@@ -600,6 +601,22 @@ config SND_SOC_AW8738
SND_SOC_SIMPLE_AMPLIFIER, but additionally allows setting the
operation mode using the Awinic-specific one-wire pulse control.
config SND_SOC_AW88395_LIB
tristate
config SND_SOC_AW88395
tristate "Soc Audio for awinic aw88395"
depends on I2C
select CRC8
select CRC32
select REGMAP_I2C
select SND_SOC_AW88395_LIB
help
this option enables support for aw88395 Smart PA.
The Awinic AW88395 is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10V
smart boost convert.
config SND_SOC_BD28623
tristate "ROHM BD28623 CODEC"
help
......
......@@ -46,6 +46,9 @@ snd-soc-ak5386-objs := ak5386.o
snd-soc-ak5558-objs := ak5558.o
snd-soc-arizona-objs := arizona.o arizona-jack.o
snd-soc-aw8738-objs := aw8738.o
snd-soc-aw88395-lib-objs := aw88395/aw88395_lib.o
snd-soc-aw88395-objs := aw88395/aw88395.o \
aw88395/aw88395_device.o
snd-soc-bd28623-objs := bd28623.o
snd-soc-bt-sco-objs := bt-sco.o
snd-soc-cpcap-objs := cpcap.o
......@@ -408,6 +411,8 @@ obj-$(CONFIG_SND_SOC_ALC5623) += snd-soc-alc5623.o
obj-$(CONFIG_SND_SOC_ALC5632) += snd-soc-alc5632.o
obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o
obj-$(CONFIG_SND_SOC_AW8738) += snd-soc-aw8738.o
obj-$(CONFIG_SND_SOC_AW88395_LIB) += snd-soc-aw88395-lib.o
obj-$(CONFIG_SND_SOC_AW88395) +=snd-soc-aw88395.o
obj-$(CONFIG_SND_SOC_BD28623) += snd-soc-bd28623.o
obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o
obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
......
// SPDX-License-Identifier: GPL-2.0-only
//
// aw883_data_type.h -- The data type of the AW88395 chip
//
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
//
// Author: Bruce zhao <zhaolei@awinic.com>
//
#ifndef __AW88395_DATA_TYPE_H__
#define __AW88395_DATA_TYPE_H__
#define PROJECT_NAME_MAX (24)
#define CUSTOMER_NAME_MAX (16)
#define CFG_VERSION_MAX (4)
#define DEV_NAME_MAX (16)
#define PROFILE_STR_MAX (32)
#define ACF_FILE_ID (0xa15f908)
enum aw_cfg_hdr_version {
AW88395_CFG_HDR_VER = 0x00000001,
AW88395_CFG_HDR_VER_V1 = 0x01000000,
};
enum aw_cfg_dde_type {
AW88395_DEV_NONE_TYPE_ID = 0xFFFFFFFF,
AW88395_DEV_TYPE_ID = 0x00000000,
AW88395_SKT_TYPE_ID = 0x00000001,
AW88395_DEV_DEFAULT_TYPE_ID = 0x00000002,
};
enum aw_sec_type {
ACF_SEC_TYPE_REG = 0,
ACF_SEC_TYPE_DSP,
ACF_SEC_TYPE_DSP_CFG,
ACF_SEC_TYPE_DSP_FW,
ACF_SEC_TYPE_HDR_REG,
ACF_SEC_TYPE_HDR_DSP_CFG,
ACF_SEC_TYPE_HDR_DSP_FW,
ACF_SEC_TYPE_MULTIPLE_BIN,
ACF_SEC_TYPE_SKT_PROJECT,
ACF_SEC_TYPE_DSP_PROJECT,
ACF_SEC_TYPE_MONITOR,
ACF_SEC_TYPE_MAX,
};
enum profile_data_type {
AW88395_DATA_TYPE_REG = 0,
AW88395_DATA_TYPE_DSP_CFG,
AW88395_DATA_TYPE_DSP_FW,
AW88395_DATA_TYPE_MAX,
};
enum aw_prof_type {
AW88395_PROFILE_MUSIC = 0,
AW88395_PROFILE_VOICE,
AW88395_PROFILE_VOIP,
AW88395_PROFILE_RINGTONE,
AW88395_PROFILE_RINGTONE_HS,
AW88395_PROFILE_LOWPOWER,
AW88395_PROFILE_BYPASS,
AW88395_PROFILE_MMI,
AW88395_PROFILE_FM,
AW88395_PROFILE_NOTIFICATION,
AW88395_PROFILE_RECEIVER,
AW88395_PROFILE_MAX,
};
enum aw_profile_status {
AW88395_PROFILE_WAIT = 0,
AW88395_PROFILE_OK,
};
struct aw_cfg_hdr {
u32 id;
char project[PROJECT_NAME_MAX];
char custom[CUSTOMER_NAME_MAX];
char version[CFG_VERSION_MAX];
u32 author_id;
u32 ddt_size;
u32 ddt_num;
u32 hdr_offset;
u32 hdr_version;
u32 reserved[3];
};
struct aw_cfg_dde {
u32 type;
char dev_name[DEV_NAME_MAX];
u16 dev_index;
u16 dev_bus;
u16 dev_addr;
u16 dev_profile;
u32 data_type;
u32 data_size;
u32 data_offset;
u32 data_crc;
u32 reserved[5];
};
struct aw_cfg_dde_v1 {
u32 type;
char dev_name[DEV_NAME_MAX];
u16 dev_index;
u16 dev_bus;
u16 dev_addr;
u16 dev_profile;
u32 data_type;
u32 data_size;
u32 data_offset;
u32 data_crc;
char dev_profile_str[PROFILE_STR_MAX];
u32 chip_id;
u32 reserved[4];
};
struct aw_sec_data_desc {
u32 len;
u8 *data;
};
struct aw_prof_desc {
u32 id;
u32 prof_st;
char *prf_str;
u32 fw_ver;
struct aw_sec_data_desc sec_desc[AW88395_DATA_TYPE_MAX];
};
struct aw_all_prof_info {
struct aw_prof_desc prof_desc[AW88395_PROFILE_MAX];
};
struct aw_prof_info {
int count;
int prof_type;
char **prof_name_list;
struct aw_prof_desc *prof_desc;
};
#endif
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