Commit 1696e6bc authored by Brian Norris's avatar Brian Norris Committed by David Woodhouse

mtd: nand: kill NAND_NO_READRDY

According to its documentation, the NAND_NO_READRDY option is always used
when autoincrement is not supported. Autoincrement support was recently
dropped, so we can drop this options as well (defaulting to "no read ready
check").
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent 63d99c0e
...@@ -805,7 +805,6 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) ...@@ -805,7 +805,6 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
chip->bbt_md = &bbt_mirror_descr; chip->bbt_md = &bbt_mirror_descr;
/* set up nand options */ /* set up nand options */
chip->options = NAND_NO_READRDY;
chip->bbt_options = NAND_BBT_USE_FLASH; chip->bbt_options = NAND_BBT_USE_FLASH;
chip->controller = &elbc_fcm_ctrl->controller; chip->controller = &elbc_fcm_ctrl->controller;
......
...@@ -805,7 +805,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) ...@@ -805,7 +805,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
out_be32(&ifc->ifc_nand.ncfgr, 0x0); out_be32(&ifc->ifc_nand.ncfgr, 0x0);
/* set up nand options */ /* set up nand options */
chip->options = NAND_NO_READRDY;
chip->bbt_options = NAND_BBT_USE_FLASH; chip->bbt_options = NAND_BBT_USE_FLASH;
......
...@@ -1565,14 +1565,6 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, ...@@ -1565,14 +1565,6 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
oobreadlen -= toread; oobreadlen -= toread;
} }
} }
if (!(chip->options & NAND_NO_READRDY)) {
/* Apply delay or wait for ready/busy pin */
if (!chip->dev_ready)
udelay(chip->chip_delay);
else
nand_wait_ready(mtd);
}
} else { } else {
memcpy(buf, chip->buffers->databuf + col, bytes); memcpy(buf, chip->buffers->databuf + col, bytes);
buf += bytes; buf += bytes;
...@@ -1837,14 +1829,6 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, ...@@ -1837,14 +1829,6 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
len = min(len, readlen); len = min(len, readlen);
buf = nand_transfer_oob(chip, buf, ops, len); buf = nand_transfer_oob(chip, buf, ops, len);
if (!(chip->options & NAND_NO_READRDY)) {
/* Apply delay or wait for ready/busy pin */
if (!chip->dev_ready)
udelay(chip->chip_delay);
else
nand_wait_ready(mtd);
}
readlen -= len; readlen -= len;
if (!readlen) if (!readlen)
break; break;
...@@ -2915,7 +2899,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, ...@@ -2915,7 +2899,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
*busw = NAND_BUSWIDTH_16; *busw = NAND_BUSWIDTH_16;
chip->options &= ~NAND_CHIPOPTIONS_MSK; chip->options &= ~NAND_CHIPOPTIONS_MSK;
chip->options |= NAND_NO_READRDY & NAND_CHIPOPTIONS_MSK;
pr_info("ONFI flash detected\n"); pr_info("ONFI flash detected\n");
return 1; return 1;
......
...@@ -70,7 +70,7 @@ struct nand_flash_dev nand_flash_ids[] = { ...@@ -70,7 +70,7 @@ struct nand_flash_dev nand_flash_ids[] = {
* These are the new chips with large page size. The pagesize and the * These are the new chips with large page size. The pagesize and the
* erasesize is determined from the extended id bytes * erasesize is determined from the extended id bytes
*/ */
#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY) #define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS
#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
/* 512 Megabit */ /* 512 Megabit */
...@@ -157,7 +157,7 @@ struct nand_flash_dev nand_flash_ids[] = { ...@@ -157,7 +157,7 @@ struct nand_flash_dev nand_flash_ids[] = {
* writes possible, but not implemented now * writes possible, but not implemented now
*/ */
{"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000,
NAND_IS_AND | NAND_NO_READRDY | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH}, NAND_IS_AND | NAND_4PAGE_ARRAY | BBT_AUTO_REFRESH},
{NULL,} {NULL,}
}; };
......
...@@ -1005,7 +1005,6 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) ...@@ -1005,7 +1005,6 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
chip->ecc.size = host->page_size; chip->ecc.size = host->page_size;
chip->ecc.strength = 1; chip->ecc.strength = 1;
chip->options |= NAND_NO_READRDY;
if (host->reg_ndcr & NDCR_DWIDTH_M) if (host->reg_ndcr & NDCR_DWIDTH_M)
chip->options |= NAND_BUSWIDTH_16; chip->options |= NAND_BUSWIDTH_16;
......
...@@ -185,12 +185,6 @@ typedef enum { ...@@ -185,12 +185,6 @@ typedef enum {
* This happens with the Renesas AG-AND chips, possibly others. * This happens with the Renesas AG-AND chips, possibly others.
*/ */
#define BBT_AUTO_REFRESH 0x00000080 #define BBT_AUTO_REFRESH 0x00000080
/*
* Chip does not require ready check on read. True
* for all large page devices, as they do not support
* autoincrement.
*/
#define NAND_NO_READRDY 0x00000100
/* Chip does not allow subpage writes */ /* Chip does not allow subpage writes */
#define NAND_NO_SUBPAGE_WRITE 0x00000200 #define NAND_NO_SUBPAGE_WRITE 0x00000200
......
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