Commit 16faf8cb authored by Mark Brown's avatar Mark Brown

ASoC: mt8365: Fix -Werror builds

Merge series from Mark Brown <broonie@kernel.org>:

Nathan reported that the newly added mt8365 drivers were causing a
number of warnings which break -Werror builds, these were only visible
on arm64 since the drivers did not have COMPILE_TEST enabled.  Fix this
and some other minor stuff I noticed while doing so.
parents 43fbb2c7 36fa259b
......@@ -301,7 +301,7 @@ config SND_SOC_MT8195_MT6359
config SND_SOC_MT8365
tristate "ASoC support for MediaTek MT8365 chip"
depends on ARCH_MEDIATEK
depends on ARCH_MEDIATEK || COMPILE_TEST
select SND_SOC_MEDIATEK
help
This adds ASoC platform driver support for MediaTek MT8365 chip
......
......@@ -295,7 +295,7 @@ int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)
return 0;
}
int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
static int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
{
if (apll1)
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
......@@ -307,7 +307,7 @@ int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
return 0;
}
int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
static int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
{
if (apll1)
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
......
......@@ -421,7 +421,6 @@ static inline u32 AutoRstThLo(unsigned int fs)
}
}
bool mt8365_afe_clk_group_48k(int sample_rate);
bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id);
bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id);
......
......@@ -170,7 +170,7 @@ bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id)
return false;
}
bool mt8365_afe_clk_group_44k(int sample_rate)
static bool mt8365_afe_clk_group_44k(int sample_rate)
{
if (sample_rate == 11025 ||
sample_rate == 22050 ||
......@@ -182,7 +182,7 @@ bool mt8365_afe_clk_group_44k(int sample_rate)
return false;
}
bool mt8365_afe_clk_group_48k(int sample_rate)
static bool mt8365_afe_clk_group_48k(int sample_rate)
{
return (!mt8365_afe_clk_group_44k(sample_rate));
}
......@@ -496,8 +496,8 @@ static int mt8365_afe_configure_cm(struct mtk_base_afe *afe,
return 0;
}
int mt8365_afe_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
static int mt8365_afe_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
......@@ -651,7 +651,6 @@ static int mt8365_afe_fe_hw_free(struct snd_pcm_substream *substream,
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8365_afe_private *afe_priv = afe->platform_priv;
int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[dai_id];
struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id];
int ret = 0;
......@@ -714,8 +713,8 @@ static int mt8365_afe_fe_prepare(struct snd_pcm_substream *substream,
return 0;
}
int mt8365_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
static int mt8365_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
......
......@@ -108,36 +108,6 @@ static void mt8365_dai_disable_dmic(struct mtk_base_afe *afe,
regmap_update_bits(afe->regmap, reg, mask, 0);
}
static const struct reg_sequence mt8365_dmic_iir_coeff[] = {
{ AFE_DMIC0_IIR_COEF_02_01, 0x00000000 },
{ AFE_DMIC0_IIR_COEF_04_03, 0x00003FB8 },
{ AFE_DMIC0_IIR_COEF_06_05, 0x3FB80000 },
{ AFE_DMIC0_IIR_COEF_08_07, 0x3FB80000 },
{ AFE_DMIC0_IIR_COEF_10_09, 0x0000C048 },
{ AFE_DMIC1_IIR_COEF_02_01, 0x00000000 },
{ AFE_DMIC1_IIR_COEF_04_03, 0x00003FB8 },
{ AFE_DMIC1_IIR_COEF_06_05, 0x3FB80000 },
{ AFE_DMIC1_IIR_COEF_08_07, 0x3FB80000 },
{ AFE_DMIC1_IIR_COEF_10_09, 0x0000C048 },
{ AFE_DMIC2_IIR_COEF_02_01, 0x00000000 },
{ AFE_DMIC2_IIR_COEF_04_03, 0x00003FB8 },
{ AFE_DMIC2_IIR_COEF_06_05, 0x3FB80000 },
{ AFE_DMIC2_IIR_COEF_08_07, 0x3FB80000 },
{ AFE_DMIC2_IIR_COEF_10_09, 0x0000C048 },
{ AFE_DMIC3_IIR_COEF_02_01, 0x00000000 },
{ AFE_DMIC3_IIR_COEF_04_03, 0x00003FB8 },
{ AFE_DMIC3_IIR_COEF_06_05, 0x3FB80000 },
{ AFE_DMIC3_IIR_COEF_08_07, 0x3FB80000 },
{ AFE_DMIC3_IIR_COEF_10_09, 0x0000C048 },
};
static int mt8365_dai_load_dmic_iir_coeff_table(struct mtk_base_afe *afe)
{
return regmap_multi_reg_write(afe->regmap,
mt8365_dmic_iir_coeff,
ARRAY_SIZE(mt8365_dmic_iir_coeff));
}
static int mt8365_dai_configure_dmic(struct mtk_base_afe *afe,
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
......
......@@ -385,7 +385,7 @@ static int mt8365_afe_set_2nd_i2s_asrc(struct mtk_base_afe *afe,
/* disable IIR coeff SRAM access */
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
COEFF_SRAM_CTRL,
(unsigned long)~COEFF_SRAM_CTRL);
~COEFF_SRAM_CTRL);
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
CLR_IIR_HISTORY | IIR_EN | IIR_STAGE_MASK,
CLR_IIR_HISTORY | IIR_EN |
......@@ -393,7 +393,7 @@ static int mt8365_afe_set_2nd_i2s_asrc(struct mtk_base_afe *afe,
} else {
/* disable IIR */
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
IIR_EN, (unsigned long)~IIR_EN);
IIR_EN, ~IIR_EN);
}
/* CON3 setting (RX OFS) */
......@@ -456,7 +456,7 @@ static int mt8365_afe_set_2nd_i2s_asrc_enable(struct mtk_base_afe *afe,
ASM_ON, ASM_ON);
else
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
ASM_ON, (unsigned long)~ASM_ON);
ASM_ON, ~ASM_ON);
return 0;
}
......
......@@ -290,9 +290,8 @@ static int mt8365_mt6357_dev_probe(struct mtk_soc_card_data *soc_card_data, bool
struct mtk_platform_card_data *card_data = soc_card_data->card_data;
struct snd_soc_card *card = card_data->card;
struct device *dev = card->dev;
struct device_node *platform_node;
struct mt8365_mt6357_priv *mach_priv;
int i, ret;
int ret;
card->dev = dev;
ret = parse_dai_link_info(card);
......
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