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Commit 194bebfe authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'at91-fixes-6.0' of... 

Merge tag 'at91-fixes-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes

AT91 fixes for 6.0

It contains:
- fixes for self-refresh on SAMA7G5 while in AT91 power management modes:
  one disabling a DDR PHY controller DLL which has been proved to be buggy
  and can introduce glitches that can cause unexpected behavior; one
  fixing the DDR PHY recalibration which cannot work for all possible
  cases (due to hardware bug) while using backup and self-refresh AT91
  power management mode;
- one defconfig fix to remove CONFIG_MICROCHIP_PIT64B from all AT91
  defconfigs;
- multiple device tree fixes for regulators to avoid having some of them
  enabled all the time and to describe min and max output ranges
  according to board capabilities.

* tag 'at91-fixes-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: at91: sama5d2_icp: don't keep vdd_other enabled all the time
  ARM: dts: at91: sama5d27_wlsom1: don't keep ldo2 enabled all the time
  ARM: dts: at91: sama7g5ek: specify proper regulator output ranges
  ARM: dts: at91: sama5d2_icp: specify proper regulator output ranges
  ARM: dts: at91: sama5d27_wlsom1: specify proper regulator output ranges
  ARM: at91: pm: fix DDR recalibration when resuming from backup and self-refresh
  ARM: at91: pm: fix self-refresh for sama7g5
  ARM: configs: at91: remove CONFIG_MICROCHIP_PIT64B

Link: https://lore.kernel.org/r/20220902085744.4193554-1-claudiu.beznea@microchip.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9a472613 3d074b75
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arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
View file @ 194bebfe
...@@ -76,8 +76,8 @@ mcp16502@5b { ...@@ -76,8 +76,8 @@ mcp16502@5b {
regulators { regulators {
vdd_3v3: VDD_IO { vdd_3v3: VDD_IO {
regulator-name = "VDD_IO"; regulator-name = "VDD_IO";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -95,8 +95,8 @@ regulator-state-mem { ...@@ -95,8 +95,8 @@ regulator-state-mem {
vddio_ddr: VDD_DDR { vddio_ddr: VDD_DDR {
regulator-name = "VDD_DDR"; regulator-name = "VDD_DDR";
regulator-min-microvolt = <600000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -118,8 +118,8 @@ regulator-state-mem { ...@@ -118,8 +118,8 @@ regulator-state-mem {
vdd_core: VDD_CORE { vdd_core: VDD_CORE {
regulator-name = "VDD_CORE"; regulator-name = "VDD_CORE";
regulator-min-microvolt = <600000>; regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -160,8 +160,8 @@ regulator-state-mem { ...@@ -160,8 +160,8 @@ regulator-state-mem {
LDO1 { LDO1 {
regulator-name = "LDO1"; regulator-name = "LDO1";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3300000>;
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
...@@ -175,9 +175,8 @@ regulator-state-mem { ...@@ -175,9 +175,8 @@ regulator-state-mem {
LDO2 { LDO2 {
regulator-name = "LDO2"; regulator-name = "LDO2";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-standby { regulator-state-standby {
regulator-on-in-suspend; regulator-on-in-suspend;
......
arch/arm/boot/dts/at91-sama5d2_icp.dts
View file @ 194bebfe
...@@ -196,8 +196,8 @@ mcp16502@5b { ...@@ -196,8 +196,8 @@ mcp16502@5b {
regulators { regulators {
vdd_io_reg: VDD_IO { vdd_io_reg: VDD_IO {
regulator-name = "VDD_IO"; regulator-name = "VDD_IO";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -215,8 +215,8 @@ regulator-state-mem { ...@@ -215,8 +215,8 @@ regulator-state-mem {
VDD_DDR { VDD_DDR {
regulator-name = "VDD_DDR"; regulator-name = "VDD_DDR";
regulator-min-microvolt = <600000>; regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -234,8 +234,8 @@ regulator-state-mem { ...@@ -234,8 +234,8 @@ regulator-state-mem {
VDD_CORE { VDD_CORE {
regulator-name = "VDD_CORE"; regulator-name = "VDD_CORE";
regulator-min-microvolt = <600000>; regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -257,7 +257,6 @@ VDD_OTHER { ...@@ -257,7 +257,6 @@ VDD_OTHER {
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1850000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby { regulator-state-standby {
regulator-on-in-suspend; regulator-on-in-suspend;
...@@ -272,8 +271,8 @@ regulator-state-mem { ...@@ -272,8 +271,8 @@ regulator-state-mem {
LDO1 { LDO1 {
regulator-name = "LDO1"; regulator-name = "LDO1";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <2500000>;
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
...@@ -287,8 +286,8 @@ regulator-state-mem { ...@@ -287,8 +286,8 @@ regulator-state-mem {
LDO2 { LDO2 {
regulator-name = "LDO2"; regulator-name = "LDO2";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3300000>;
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
......
arch/arm/boot/dts/at91-sama7g5ek.dts
View file @ 194bebfe
...@@ -244,8 +244,8 @@ mcp16502@5b { ...@@ -244,8 +244,8 @@ mcp16502@5b {
regulators { regulators {
vdd_3v3: VDD_IO { vdd_3v3: VDD_IO {
regulator-name = "VDD_IO"; regulator-name = "VDD_IO";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -264,8 +264,8 @@ regulator-state-mem { ...@@ -264,8 +264,8 @@ regulator-state-mem {
vddioddr: VDD_DDR { vddioddr: VDD_DDR {
regulator-name = "VDD_DDR"; regulator-name = "VDD_DDR";
regulator-min-microvolt = <1300000>; regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1450000>; regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -285,8 +285,8 @@ regulator-state-mem { ...@@ -285,8 +285,8 @@ regulator-state-mem {
vddcore: VDD_CORE { vddcore: VDD_CORE {
regulator-name = "VDD_CORE"; regulator-name = "VDD_CORE";
regulator-min-microvolt = <1100000>; regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1150000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
...@@ -306,7 +306,7 @@ regulator-state-mem { ...@@ -306,7 +306,7 @@ regulator-state-mem {
vddcpu: VDD_OTHER { vddcpu: VDD_OTHER {
regulator-name = "VDD_OTHER"; regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-ramp-delay = <3125>; regulator-ramp-delay = <3125>;
...@@ -326,8 +326,8 @@ regulator-state-mem { ...@@ -326,8 +326,8 @@ regulator-state-mem {
vldo1: LDO1 { vldo1: LDO1 {
regulator-name = "LDO1"; regulator-name = "LDO1";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <1800000>;
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
......
arch/arm/configs/at91_dt_defconfig
View file @ 194bebfe
...@@ -196,7 +196,6 @@ CONFIG_RTC_DRV_AT91SAM9=y ...@@ -196,7 +196,6 @@ CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y CONFIG_AT_HDMAC=y
CONFIG_AT_XDMAC=y CONFIG_AT_XDMAC=y
CONFIG_MICROCHIP_PIT64B=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y CONFIG_IIO=y
CONFIG_AT91_ADC=y CONFIG_AT91_ADC=y
......
arch/arm/configs/sama7_defconfig
View file @ 194bebfe
...@@ -188,7 +188,6 @@ CONFIG_RTC_DRV_AT91SAM9=y ...@@ -188,7 +188,6 @@ CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_AT_XDMAC=y CONFIG_AT_XDMAC=y
CONFIG_STAGING=y CONFIG_STAGING=y
CONFIG_MICROCHIP_PIT64B=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y CONFIG_IIO=y
CONFIG_IIO_SW_TRIGGER=y CONFIG_IIO_SW_TRIGGER=y
......
arch/arm/mach-at91/pm.c
View file @ 194bebfe
...@@ -541,9 +541,41 @@ extern u32 at91_pm_suspend_in_sram_sz; ...@@ -541,9 +541,41 @@ extern u32 at91_pm_suspend_in_sram_sz;
static int at91_suspend_finish(unsigned long val) static int at91_suspend_finish(unsigned long val)
{ {
unsigned char modified_gray_code[] = {
0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
0x10, 0x11,
};
unsigned int tmp, index;
int i; int i;
if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
/*
* Bootloader will perform DDR recalibration and will try to
* restore the ZQ0SR0 with the value saved here. But the
* calibration is buggy and restoring some values from ZQ0SR0
* is forbidden and risky thus we need to provide processed
* values for these (modified gray code values).
*/
tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
/* Store pull-down output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
/* Store pull-up output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
/* Store pull-down on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
/* Store pull-up on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
/* /*
* The 1st 8 words of memory might get corrupted in the process * The 1st 8 words of memory might get corrupted in the process
* of DDR PHY recalibration; it is saved here in securam and it * of DDR PHY recalibration; it is saved here in securam and it
...@@ -1066,10 +1098,6 @@ static int __init at91_pm_backup_init(void) ...@@ -1066,10 +1098,6 @@ static int __init at91_pm_backup_init(void)
of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
if (!located) if (!located)
goto securam_fail; goto securam_fail;
/* DDR3PHY_ZQ0SR0 */
soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
0x188);
} }
return 0; return 0;
......
arch/arm/mach-at91/pm_suspend.S
View file @ 194bebfe
...@@ -172,9 +172,15 @@ sr_ena_2: ...@@ -172,9 +172,15 @@ sr_ena_2:
/* Put DDR PHY's DLL in bypass mode for non-backup modes. */ /* Put DDR PHY's DLL in bypass mode for non-backup modes. */
cmp r7, #AT91_PM_BACKUP cmp r7, #AT91_PM_BACKUP
beq sr_ena_3 beq sr_ena_3
ldr tmp1, [r3, #DDR3PHY_PIR]
orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP /* Disable DX DLLs. */
str tmp1, [r3, #DDR3PHY_PIR] ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
str tmp1, [r3, #DDR3PHY_DX0DLLCR]
ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
str tmp1, [r3, #DDR3PHY_DX1DLLCR]
sr_ena_3: sr_ena_3:
/* Power down DDR PHY data receivers. */ /* Power down DDR PHY data receivers. */
...@@ -221,10 +227,14 @@ sr_ena_3: ...@@ -221,10 +227,14 @@ sr_ena_3:
bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
str tmp1, [r3, #DDR3PHY_DSGCR] str tmp1, [r3, #DDR3PHY_DSGCR]
/* Take DDR PHY's DLL out of bypass mode. */ /* Enable DX DLLs. */
ldr tmp1, [r3, #DDR3PHY_PIR] ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
str tmp1, [r3, #DDR3PHY_PIR] str tmp1, [r3, #DDR3PHY_DX0DLLCR]
ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
str tmp1, [r3, #DDR3PHY_DX1DLLCR]
/* Enable quasi-dynamic programming. */ /* Enable quasi-dynamic programming. */
mov tmp1, #0 mov tmp1, #0
......
include/soc/at91/sama7-ddr.h
View file @ 194bebfe
...@@ -38,6 +38,14 @@ ...@@ -38,6 +38,14 @@
#define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */ #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
#define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */ #define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */
#define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
#define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
#define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
#define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
#define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */
#define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */
#define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */
/* UDDRC */ /* UDDRC */
#define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */ #define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */
......
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