Commit 1a0041b8 authored by Alex Deucher's avatar Alex Deucher

drm/radeon: add pci config hard reset

This is used to hard reset the asic.  If a soft
reset is not able to reset things, a hard reset
can be used.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 363eb0b4
...@@ -140,6 +140,9 @@ extern int radeon_hard_reset; ...@@ -140,6 +140,9 @@ extern int radeon_hard_reset;
#define RADEON_VA_RESERVED_SIZE (8 << 20) #define RADEON_VA_RESERVED_SIZE (8 << 20)
#define RADEON_IB_VM_MAX_SIZE (64 << 10) #define RADEON_IB_VM_MAX_SIZE (64 << 10)
/* hard reset data */
#define RADEON_ASIC_RESET_DATA 0x39d5e86b
/* reset flags */ /* reset flags */
#define RADEON_RESET_GFX (1 << 0) #define RADEON_RESET_GFX (1 << 0)
#define RADEON_RESET_COMPUTE (1 << 1) #define RADEON_RESET_COMPUTE (1 << 1)
...@@ -2675,6 +2678,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); ...@@ -2675,6 +2678,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
/* Common functions */ /* Common functions */
/* AGP */ /* AGP */
extern int radeon_gpu_reset(struct radeon_device *rdev); extern int radeon_gpu_reset(struct radeon_device *rdev);
extern void radeon_pci_config_reset(struct radeon_device *rdev);
extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
extern void radeon_agp_disable(struct radeon_device *rdev); extern void radeon_agp_disable(struct radeon_device *rdev);
extern int radeon_modeset_init(struct radeon_device *rdev); extern int radeon_modeset_init(struct radeon_device *rdev);
......
...@@ -144,6 +144,11 @@ void radeon_program_register_sequence(struct radeon_device *rdev, ...@@ -144,6 +144,11 @@ void radeon_program_register_sequence(struct radeon_device *rdev,
} }
} }
void radeon_pci_config_reset(struct radeon_device *rdev)
{
pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
}
/** /**
* radeon_surface_init - Clear GPU surface registers. * radeon_surface_init - Clear GPU surface registers.
* *
......
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