SPARC: Beginning of converting Sparc serial drivers to UART layer.

drivers/serial/sun.c

+/* sun.c
+ *
+ * Generic SUN serial/kbd/ms layer.  Based entirely
+ * upon drivers/sbus/char/sunserial.c which is:
+ *
+ * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
+ *
+ * Port to new UART layer is:
+ *
+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/kbd_diacr.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+
+#include <asm/oplib.h>
+
+#include "sun.h"
+
+int serial_console;
+int stop_a_enabled = 1;
+
+int __init con_is_present(void)
+{
+	return serial_console ? 0 : 1;
+}
+
+static void __init nop_rs_kgdb_hook(int channel)
+{ printk("Oops: nop_rs_kgdb_hook called\n"); }
+
+static void nop_rs_change_mouse_baud(int baud)
+{ printk("Oops: nop_rs_change_mouse_baud called\n"); }
+
+static int nop_rs_read_proc(char *page, char **start, off_t off, int count,
+			    int *eof, void *data)
+{ printk("Oops: nop_rs_read_proc called\n"); return 0; }
+
+struct sunserial_operations rs_ops = {
+	0,
+	nop_rs_kgdb_hook,
+	nop_rs_change_mouse_baud,
+	nop_rs_read_proc
+};
+
+static int __init serial_sun_init(void)
+{
+	struct sun_initfunc *init;
+
+	init = rs_ops.rs_init;
+	while (init) {
+		(void) init->init();
+		init = init->next;
+	}
+
+	return 0;
+}
+
+static void __exit serial_sun_exit(void)
+{
+}
+
+module_init(serial_sun_init);
+module_exit(serial_sun_exit);
+
+void __init rs_kgdb_hook(int channel)
+{ rs_ops.rs_kgdb_hook(channel); }
+
+void rs_change_mouse_baud(int baud)
+{ rs_ops.rs_change_mouse_baud(baud); }
+
+int rs_read_proc(char *page, char **start, off_t off, int count,
+		 int *eof, void *data)
+{ return rs_ops.rs_read_proc(page, start, off, count, eof, data); }
+
+static void nop_compute_shiftstate (void)
+{ printk("Oops: nop_compute_shiftstate called\n"); }
+
+static void nop_setledstate (struct kbd_struct *kbd, unsigned int ledstate)
+{ printk("Oops: nop_setledstate called\n"); }
+
+static unsigned char nop_getledstate (void)
+{ printk("Oops: nop_getledstate called\n"); return 0; }
+
+static int nop_setkeycode (unsigned int scancode, unsigned int keycode)
+{ printk("Oops: nop_setkeycode called\n"); return -EINVAL; }
+
+static int nop_getkeycode (unsigned int scancode)
+{ printk("Oops: nop_getkeycode called\n"); return -EINVAL; }
+
+struct sunkbd_operations kbd_ops = {
+	0,
+	nop_compute_shiftstate,
+	nop_setledstate,
+	nop_getledstate,
+	nop_setkeycode,
+	nop_getkeycode
+};
+
+#ifdef CONFIG_USB
+extern void pci_compute_shiftstate(void);
+extern int pci_setkeycode(unsigned int, unsigned int);
+extern int pci_getkeycode(unsigned int);
+extern void pci_setledstate(struct kbd_struct *, unsigned int);
+extern unsigned char pci_getledstate(void);
+extern int pcikbd_init(void);
+#endif
+
+int kbd_init(void)
+{
+	struct sun_initfunc *init;
+	int err = -ENODEV;
+
+	init = kbd_ops.kbd_init;
+	while (init) {
+		err = init->init();
+		init = init->next;
+	}
+#ifdef CONFIG_USB
+	if (!serial_console &&
+	    kbd_ops.compute_shiftstate == nop_compute_shiftstate) {
+		printk("kbd_init: Assuming USB keyboard.\n");
+		kbd_ops.compute_shiftstate = pci_compute_shiftstate;
+		kbd_ops.setledstate = pci_setledstate;
+		kbd_ops.getledstate = pci_getledstate;
+		kbd_ops.setkeycode = pci_setkeycode;
+		kbd_ops.getkeycode = pci_getkeycode;
+		pcikbd_init();
+	}
+#endif
+	return err;
+}
+
+void compute_shiftstate(void)
+{ kbd_ops.compute_shiftstate(); }
+
+void setledstate(struct kbd_struct *kbd, unsigned int ledstate)
+{ kbd_ops.setledstate(kbd, ledstate); }
+
+unsigned char getledstate(void)
+{ return kbd_ops.getledstate(); }
+
+int setkeycode(unsigned int scancode, unsigned int keycode)
+{ return kbd_ops.setkeycode(scancode, keycode); }
+
+int getkeycode(unsigned int scancode)
+{ return kbd_ops.getkeycode(scancode); }
+
+void * __init sunserial_alloc_bootmem(unsigned long size)
+{
+	void *ret;
+
+	ret = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
+	if (ret != NULL)
+		memset(ret, 0, size);
+
+	return ret;
+}
+
+void
+sunserial_setsun_initfunc(int (*init) (void))
+{
+	struct sun_initfunc *rs_initfunc;
+
+	rs_initfunc = sunserial_alloc_bootmem(sizeof(*rs_initfunc));
+	if (rs_initfunc == NULL) {
+		prom_printf("sunserial_setsun_initfunc: Cannot alloc sun_initfunc.\n");
+		prom_halt();
+	}
+
+	rs_initfunc->init = init;
+	rs_initfunc->next = rs_ops.rs_init;
+	rs_ops.rs_init = rs_initfunc;
+}
+
+void
+sunserial_console_termios(struct console *con)
+{
+	char mode[16], buf[16], *s;
+	char *mode_prop = "ttyX-mode";
+	char *cd_prop = "ttyX-ignore-cd";
+	char *dtr_prop = "ttyX-rts-dtr-off";
+	int baud, bits, stop, cflag;
+	char parity;
+	int carrier = 0;
+	int rtsdtr = 1;
+	int topnd, nd;
+
+	if (!serial_console)
+		return;
+
+	if (serial_console == 1) {
+		mode_prop[3] = 'a';
+		cd_prop[3] = 'a';
+		dtr_prop[3] = 'a';
+	} else {
+		mode_prop[3] = 'b';
+		cd_prop[3] = 'b';
+		dtr_prop[3] = 'b';
+	}
+
+	topnd = prom_getchild(prom_root_node);
+	nd = prom_searchsiblings(topnd, "options");
+	if (!nd) {
+		strcpy(mode, "9600,8,n,1,-");
+		goto no_options;
+	}
+
+	if (!prom_node_has_property(nd, mode_prop)) {
+		strcpy(mode, "9600,8,n,1,-");
+		goto no_options;
+	}
+
+	memset(mode, 0, sizeof(mode));
+	prom_getstring(nd, mode_prop, mode, sizeof(mode));
+
+	if (prom_node_has_property(nd, cd_prop)) {
+		memset(buf, 0, sizeof(buf));
+		prom_getstring(nd, cd_prop, buf, sizeof(buf));
+		if (!strcmp(buf, "false"))
+			carrier = 1;
+
+		/* XXX: this is unused below. */
+	}
+
+	if (prom_node_has_property(nd, cd_prop)) {
+		memset(buf, 0, sizeof(buf));
+		prom_getstring(nd, cd_prop, buf, sizeof(buf));
+		if (!strcmp(buf, "false"))
+			rtsdtr = 0;
+
+		/* XXX: this is unused below. */
+	}
+
+no_options:
+	cflag = CREAD | HUPCL | CLOCAL;
+
+	s = mode;
+	baud = simple_strtoul(s, 0, 0);
+	s = strchr(s, ',');
+	bits = simple_strtoul(++s, 0, 0);
+	s = strchr(s, ',');
+	parity = *(++s);
+	s = strchr(s, ',');
+	stop = simple_strtoul(++s, 0, 0);
+	s = strchr(s, ',');
+	/* XXX handshake is not handled here. */
+
+	switch (baud) {
+		case 150: cflag |= B150; break;
+		case 300: cflag |= B300; break;
+		case 600: cflag |= B600; break;
+		case 1200: cflag |= B1200; break;
+		case 2400: cflag |= B2400; break;
+		case 4800: cflag |= B4800; break;
+		case 9600: cflag |= B9600; break;
+		case 19200: cflag |= B19200; break;
+		case 38400: cflag |= B38400; break;
+		default: baud = 9600; cflag |= B9600; break;
+	}
+
+	switch (bits) {
+		case 5: cflag |= CS5; break;
+		case 6: cflag |= CS6; break;
+		case 7: cflag |= CS7; break;
+		case 8: cflag |= CS8; break;
+		default: cflag |= CS8; break;
+	}
+
+	switch (parity) {
+		case 'o': cflag |= (PARENB | PARODD); break;
+		case 'e': cflag |= PARENB; break;
+		case 'n': default: break;
+	}
+
+	switch (stop) {
+		case 2: cflag |= CSTOPB; break;
+		case 1: default: break;
+	}
+
+	con->cflag = cflag;
+}
+
+void
+sunkbd_setsun_initfunc(int (*init)(void))
+{
+	struct sun_initfunc *kbd_initfunc;
+
+	kbd_initfunc = sunserial_alloc_bootmem(sizeof(*kbd_initfunc));
+	if (kbd_initfunc == NULL) {
+		prom_printf("sunkbd_setsun_initfunc: Cannot alloc sun_initfunc.\n");
+		prom_halt();
+	}
+
+	kbd_initfunc->init = init;
+	kbd_initfunc->next = kbd_ops.kbd_init;
+	kbd_ops.kbd_init = kbd_initfunc;
+}
+
+#ifdef CONFIG_PCI
+void
+sunkbd_install_keymaps(ushort **src_key_maps, unsigned int src_keymap_count,
+		       char *src_func_buf, char **src_func_table,
+		       int src_funcbufsize, int src_funcbufleft,
+		       struct kbdiacr *src_accent_table,
+		       unsigned int src_accent_table_size)
+{
+	extern unsigned int keymap_count;
+	int i, j;
+
+	for (i = 0; i < MAX_NR_KEYMAPS; i++) {
+		if (src_key_maps[i]) {
+			if (!key_maps[i]) {
+				key_maps[i] = (ushort *)
+					sunserial_alloc_bootmem(NR_KEYS * sizeof(ushort));
+				if (key_maps[i] == NULL) {
+					prom_printf("sunkbd_install_keymaps: "
+						    "Cannot alloc key_map(%d).\n", i);
+					prom_halt();
+				}
+			}
+			for (j = 0; j < NR_KEYS; j++)
+				key_maps[i][j] = src_key_maps[i][j];
+		}
+		key_maps[i] = src_key_maps[i];
+	}
+	keymap_count = src_keymap_count;
+
+	for (i = 0; i < MAX_NR_FUNC; i++)
+		func_table[i] = src_func_table[i];
+	funcbufptr = src_func_buf;
+	funcbufsize = src_funcbufsize;
+	funcbufleft = src_funcbufleft;
+
+	for (i = 0; i < MAX_DIACR; i++)
+		accent_table[i] = src_accent_table[i];
+	accent_table_size = src_accent_table_size;
+}
+#endif
+
+extern int sunsu_probe(void);
+extern int sunzilog_probe(void);
+#ifdef CONFIG_SAB82532
+extern int sab82532_probe(void);
+#endif
+#ifdef CONFIG_PCI
+extern int ps2kbd_probe(void);
+#endif
+
+/* This is called by the sparc32/sparc64 MM init layer right after
+ * the bootmem allocator has been setup and is ready to use.
+ */
+void __init sun_serial_setup(void)
+{
+	int ret = 1;
+	
+#if defined(CONFIG_PCI) && !defined(CONFIG_SPARC64)
+	/*
+	 * Probing sequence on sparc differs from sparc64.
+	 * Keyboard is probed ahead of su because we want su function
+	 * when keyboard is active. su is probed ahead of zs in order to
+	 * get console on MrCoffee with fine but disconnected zs.
+	 */
+	if (!serial_console)
+		ps2kbd_probe();
+	if (sunsu_probe() == 0)
+		return;
+#endif
+
+	if (sunzilog_probe() == 0)
+		return;
+		
+#ifdef CONFIG_SAB82532
+	ret = sab82532_probe();
+#endif
+
+#if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
+	/*
+	 * Keyboard serial devices.
+	 *
+	 * Well done, Sun, prom_devopen("/pci@1f,4000/ebus@1/su@14,3083f8")
+	 * hangs the machine if no keyboard is connected to the device...
+	 * All PCI PROMs seem to do this, I have seen this on the Ultra 450
+	 * with version 3.5 PROM, and on the Ultra/AX with 3.1.5 PROM.
+	 *
+	 * So be very careful not to probe for keyboards if we are on a
+	 * serial console.
+	 */
+	if (!serial_console)
+		ps2kbd_probe();
+	if (sunsu_probe() == 0)
+		return;
+#endif
+
+	if (!ret)
+		return;
+		
+#ifdef CONFIG_SPARC64
+	{	extern int this_is_starfire;
+		/* Hello, Starfire. Pleased to meet you :) */
+		if (this_is_starfire != 0)
+			return;
+	}
+#endif
+
+	prom_printf("No serial devices found, bailing out.\n");
+	prom_halt();
+}

drivers/serial/sun.h

+/* sun.h
+ *
+ * Generic SUN serial/kbd/ms layer.  Based entirely
+ * upon drivers/sbus/char/sunserial.h which is:
+ *
+ * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
+ *
+ * Port to new UART layer is:
+ *
+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _SERIAL_SUN_H
+#define _SERIAL_SUN_H
+
+#include <linux/config.h>
+
+struct sun_initfunc {
+	int			(*init) (void);
+	struct sun_initfunc	*next;
+};
+
+struct sunserial_operations {
+	struct sun_initfunc	*rs_init;
+	void		(*rs_kgdb_hook) (int);
+	void		(*rs_change_mouse_baud) (int);
+	int		(*rs_read_proc) (char *, char **, off_t, int, int *, void *);
+};
+
+struct sunkbd_operations {
+	struct sun_initfunc	*kbd_init;
+	void		(*compute_shiftstate) (void);
+	void		(*setledstate) (struct kbd_struct *, unsigned int);
+	unsigned char	(*getledstate) (void);
+	int		(*setkeycode) (unsigned int, unsigned int);
+	int		(*getkeycode) (unsigned int);
+};
+
+extern struct sunserial_operations rs_ops;
+extern struct sunkbd_operations kbd_ops;
+
+extern void sunserial_setinitfunc(int (*) (void));
+extern void sunkbd_setinitfunc(int (*) (void));
+
+extern int serial_console;
+extern int stop_a_enabled;
+extern void sunserial_console_termios(struct console *);
+
+#ifdef CONFIG_PCI
+extern void sunkbd_install_keymaps(ushort **, unsigned int, char *,
+				   char **, int, int, struct kbdiacr *,
+				   unsigned int);
+#endif
+
+#endif /* !(_SERIAL_SUN_H) */

drivers/serial/sunzilog.h

+#ifndef _SUNZILOG_H
+#define _SUNZILOG_H
+
+struct zilog_channel {
+	volatile unsigned char control;
+	volatile unsigned char __pad1;
+	volatile unsigned char data;
+	volatile unsigned char __pad2;
+};
+
+struct zilog_layout {
+	struct zilog_channel channelB;
+	struct zilog_channel channelA;
+};
+
+#define NUM_ZSREGS    16
+
+/* Conversion routines to/from brg time constants from/to bits
+ * per second.
+ */
+#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
+#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
+
+/* The Zilog register set */
+
+#define	FLAG	0x7e
+
+/* Write Register 0 */
+#define	R0	0		/* Register selects */
+#define	R1	1
+#define	R2	2
+#define	R3	3
+#define	R4	4
+#define	R5	5
+#define	R6	6
+#define	R7	7
+#define	R8	8
+#define	R9	9
+#define	R10	10
+#define	R11	11
+#define	R12	12
+#define	R13	13
+#define	R14	14
+#define	R15	15
+
+#define	NULLCODE	0	/* Null Code */
+#define	POINT_HIGH	0x8	/* Select upper half of registers */
+#define	RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
+#define	SEND_ABORT	0x18	/* HDLC Abort */
+#define	RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
+#define	RES_Tx_P	0x28	/* Reset TxINT Pending */
+#define	ERR_RES		0x30	/* Error Reset */
+#define	RES_H_IUS	0x38	/* Reset highest IUS */
+
+#define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
+#define	RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
+#define	RES_EOM_L	0xC0	/* Reset EOM latch */
+
+/* Write Register 1 */
+
+#define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
+#define	TxINT_ENAB	0x2	/* Tx Int Enable */
+#define	PAR_SPEC	0x4	/* Parity is special condition */
+
+#define	RxINT_DISAB	0	/* Rx Int Disable */
+#define	RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
+#define	INT_ALL_Rx	0x10	/* Int on all Rx Characters or error */
+#define	INT_ERR_Rx	0x18	/* Int on error only */
+#define RxINT_MASK	0x18
+
+#define	WT_RDY_RT	0x20	/* Wait/Ready on R/T */
+#define	WT_FN_RDYFN	0x40	/* Wait/FN/Ready FN */
+#define	WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
+
+/* Write Register #2 (Interrupt Vector) */
+
+/* Write Register 3 */
+
+#define	RxENAB  	0x1	/* Rx Enable */
+#define	SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
+#define	ADD_SM		0x4	/* Address Search Mode (SDLC) */
+#define	RxCRC_ENAB	0x8	/* Rx CRC Enable */
+#define	ENT_HM		0x10	/* Enter Hunt Mode */
+#define	AUTO_ENAB	0x20	/* Auto Enables */
+#define	Rx5		0x0	/* Rx 5 Bits/Character */
+#define	Rx7		0x40	/* Rx 7 Bits/Character */
+#define	Rx6		0x80	/* Rx 6 Bits/Character */
+#define	Rx8		0xc0	/* Rx 8 Bits/Character */
+#define RxN_MASK	0xc0
+
+/* Write Register 4 */
+
+#define	PAR_ENAB	0x1	/* Parity Enable */
+#define	PAR_EVEN	0x2	/* Parity Even/Odd* */
+
+#define	SYNC_ENAB	0	/* Sync Modes Enable */
+#define	SB1		0x4	/* 1 stop bit/char */
+#define	SB15		0x8	/* 1.5 stop bits/char */
+#define	SB2		0xc	/* 2 stop bits/char */
+
+#define	MONSYNC		0	/* 8 Bit Sync character */
+#define	BISYNC		0x10	/* 16 bit sync character */
+#define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
+#define	EXTSYNC		0x30	/* External Sync Mode */
+
+#define	X1CLK		0x0	/* x1 clock mode */
+#define	X16CLK		0x40	/* x16 clock mode */
+#define	X32CLK		0x80	/* x32 clock mode */
+#define	X64CLK		0xC0	/* x64 clock mode */
+#define XCLK_MASK	0xC0
+
+/* Write Register 5 */
+
+#define	TxCRC_ENAB	0x1	/* Tx CRC Enable */
+#define	RTS		0x2	/* RTS */
+#define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
+#define	TxENAB		0x8	/* Tx Enable */
+#define	SND_BRK		0x10	/* Send Break */
+#define	Tx5		0x0	/* Tx 5 bits (or less)/character */
+#define	Tx7		0x20	/* Tx 7 bits/character */
+#define	Tx6		0x40	/* Tx 6 bits/character */
+#define	Tx8		0x60	/* Tx 8 bits/character */
+#define TxN_MASK	0x60
+#define	DTR		0x80	/* DTR */
+
+/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
+
+/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
+
+/* Write Register 8 (transmit buffer) */
+
+/* Write Register 9 (Master interrupt control) */
+#define	VIS	1	/* Vector Includes Status */
+#define	NV	2	/* No Vector */
+#define	DLC	4	/* Disable Lower Chain */
+#define	MIE	8	/* Master Interrupt Enable */
+#define	STATHI	0x10	/* Status high */
+#define	NORESET	0	/* No reset on write to R9 */
+#define	CHRB	0x40	/* Reset channel B */
+#define	CHRA	0x80	/* Reset channel A */
+#define	FHWRES	0xc0	/* Force hardware reset */
+
+/* Write Register 10 (misc control bits) */
+#define	BIT6	1	/* 6 bit/8bit sync */
+#define	LOOPMODE 2	/* SDLC Loop mode */
+#define	ABUNDER	4	/* Abort/flag on SDLC xmit underrun */
+#define	MARKIDLE 8	/* Mark/flag on idle */
+#define	GAOP	0x10	/* Go active on poll */
+#define	NRZ	0	/* NRZ mode */
+#define	NRZI	0x20	/* NRZI mode */
+#define	FM1	0x40	/* FM1 (transition = 1) */
+#define	FM0	0x60	/* FM0 (transition = 0) */
+#define	CRCPS	0x80	/* CRC Preset I/O */
+
+/* Write Register 11 (Clock Mode control) */
+#define	TRxCXT	0	/* TRxC = Xtal output */
+#define	TRxCTC	1	/* TRxC = Transmit clock */
+#define	TRxCBR	2	/* TRxC = BR Generator Output */
+#define	TRxCDP	3	/* TRxC = DPLL output */
+#define	TRxCOI	4	/* TRxC O/I */
+#define	TCRTxCP	0	/* Transmit clock = RTxC pin */
+#define	TCTRxCP	8	/* Transmit clock = TRxC pin */
+#define	TCBR	0x10	/* Transmit clock = BR Generator output */
+#define	TCDPLL	0x18	/* Transmit clock = DPLL output */
+#define	RCRTxCP	0	/* Receive clock = RTxC pin */
+#define	RCTRxCP	0x20	/* Receive clock = TRxC pin */
+#define	RCBR	0x40	/* Receive clock = BR Generator output */
+#define	RCDPLL	0x60	/* Receive clock = DPLL output */
+#define	RTxCX	0x80	/* RTxC Xtal/No Xtal */
+
+/* Write Register 12 (lower byte of baud rate generator time constant) */
+
+/* Write Register 13 (upper byte of baud rate generator time constant) */
+
+/* Write Register 14 (Misc control bits) */
+#define	BRENAB 	1	/* Baud rate generator enable */
+#define	BRSRC	2	/* Baud rate generator source */
+#define	DTRREQ	4	/* DTR/Request function */
+#define	AUTOECHO 8	/* Auto Echo */
+#define	LOOPBAK	0x10	/* Local loopback */
+#define	SEARCH	0x20	/* Enter search mode */
+#define	RMC	0x40	/* Reset missing clock */
+#define	DISDPLL	0x60	/* Disable DPLL */
+#define	SSBR	0x80	/* Set DPLL source = BR generator */
+#define	SSRTxC	0xa0	/* Set DPLL source = RTxC */
+#define	SFMM	0xc0	/* Set FM mode */
+#define	SNRZI	0xe0	/* Set NRZI mode */
+
+/* Write Register 15 (external/status interrupt control) */
+#define	ZCIE	2	/* Zero count IE */
+#define	DCDIE	8	/* DCD IE */
+#define	SYNCIE	0x10	/* Sync/hunt IE */
+#define	CTSIE	0x20	/* CTS IE */
+#define	TxUIE	0x40	/* Tx Underrun/EOM IE */
+#define	BRKIE	0x80	/* Break/Abort IE */
+
+
+/* Read Register 0 */
+#define	Rx_CH_AV	0x1	/* Rx Character Available */
+#define	ZCOUNT		0x2	/* Zero count */
+#define	Tx_BUF_EMP	0x4	/* Tx Buffer empty */
+#define	DCD		0x8	/* DCD */
+#define	SYNC		0x10	/* Sync/hunt */
+#define	CTS		0x20	/* CTS */
+#define	TxEOM		0x40	/* Tx underrun */
+#define	BRK_ABRT	0x80	/* Break/Abort */
+
+/* Read Register 1 */
+#define	ALL_SNT		0x1	/* All sent */
+/* Residue Data for 8 Rx bits/char programmed */
+#define	RES3		0x8	/* 0/3 */
+#define	RES4		0x4	/* 0/4 */
+#define	RES5		0xc	/* 0/5 */
+#define	RES6		0x2	/* 0/6 */
+#define	RES7		0xa	/* 0/7 */
+#define	RES8		0x6	/* 0/8 */
+#define	RES18		0xe	/* 1/8 */
+#define	RES28		0x0	/* 2/8 */
+/* Special Rx Condition Interrupts */
+#define	PAR_ERR		0x10	/* Parity error */
+#define	Rx_OVR		0x20	/* Rx Overrun Error */
+#define	CRC_ERR		0x40	/* CRC/Framing Error */
+#define	END_FR		0x80	/* End of Frame (SDLC) */
+
+/* Read Register 2 (channel b only) - Interrupt vector */
+#define CHB_Tx_EMPTY	0x00
+#define CHB_EXT_STAT	0x02
+#define CHB_Rx_AVAIL	0x04
+#define CHB_SPECIAL	0x06
+#define CHA_Tx_EMPTY	0x08
+#define CHA_EXT_STAT	0x0a
+#define CHA_Rx_AVAIL	0x0c
+#define CHA_SPECIAL	0x0e
+#define STATUS_MASK	0x0e
+
+/* Read Register 3 (interrupt pending register) ch a only */
+#define	CHBEXT	0x1		/* Channel B Ext/Stat IP */
+#define	CHBTxIP	0x2		/* Channel B Tx IP */
+#define	CHBRxIP	0x4		/* Channel B Rx IP */
+#define	CHAEXT	0x8		/* Channel A Ext/Stat IP */
+#define	CHATxIP	0x10		/* Channel A Tx IP */
+#define	CHARxIP	0x20		/* Channel A Rx IP */
+
+/* Read Register 8 (receive data register) */
+
+/* Read Register 10  (misc status bits) */
+#define	ONLOOP	2		/* On loop */
+#define	LOOPSEND 0x10		/* Loop sending */
+#define	CLK2MIS	0x40		/* Two clocks missing */
+#define	CLK1MIS	0x80		/* One clock missing */
+
+/* Read Register 12 (lower byte of baud rate generator constant) */
+
+/* Read Register 13 (upper byte of baud rate generator constant) */
+
+/* Read Register 15 (value of WR 15) */
+
+/* Misc macros */
+#define ZS_CLEARERR(channel)    do { sbus_writeb(ERR_RES, &channel->control); \
+				     udelay(5); } while(0)
+
+#define ZS_CLEARSTAT(channel)   do { sbus_writeb(RES_EXT_INT, &channel->control); \
+				     udelay(5); } while(0)
+
+#define ZS_CLEARFIFO(channel)   do { sbus_readb(&channel->data); \
+				     udelay(2); \
+				     sbus_readb(&channel->data); \
+				     udelay(2); \
+				     sbus_readb(&channel->data); \
+				     udelay(2); } while(0)
+
+#endif /* _SUNZILOG_H */