Commit 1a78d937 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar

perf/x86/intel: Streamline LBR MSR handling in PMI

The perf PMI currently does unnecessary MSR accesses when
LBRs are enabled. We use LBR freezing, or when in callstack
mode force the LBRs to only filter on ring 3.

So there is no need to disable the LBRs explicitely in the
PMI handler.

Also we always unnecessarily rewrite LBR_SELECT in the LBR
handler, even though it can never change.

 5)               |  /* write_msr: MSR_LBR_SELECT(1c8), value 0 */
 5)               |  /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */
 5)               |  /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */
 5)               |  /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 70000000f */
 5)               |  /* write_msr: MSR_CORE_PERF_GLOBAL_CTRL(38f), value 0 */
 5)               |  /* write_msr: MSR_LBR_SELECT(1c8), value 0 */
 5)               |  /* read_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */
 5)               |  /* write_msr: MSR_IA32_DEBUGCTLMSR(1d9), value 1801 */

This patch:

  - Avoids disabling already frozen LBRs unnecessarily in the PMI
  - Avoids changing LBR_SELECT in the PMI
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1426871484-21285-1-git-send-email-andi@firstfloor.orgSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 15fde110
...@@ -870,7 +870,7 @@ void intel_pmu_lbr_enable(struct perf_event *event); ...@@ -870,7 +870,7 @@ void intel_pmu_lbr_enable(struct perf_event *event);
void intel_pmu_lbr_disable(struct perf_event *event); void intel_pmu_lbr_disable(struct perf_event *event);
void intel_pmu_lbr_enable_all(void); void intel_pmu_lbr_enable_all(bool pmi);
void intel_pmu_lbr_disable_all(void); void intel_pmu_lbr_disable_all(void);
......
...@@ -1244,7 +1244,10 @@ static __initconst const u64 slm_hw_cache_event_ids ...@@ -1244,7 +1244,10 @@ static __initconst const u64 slm_hw_cache_event_ids
}, },
}; };
static void intel_pmu_disable_all(void) /*
* Use from PMIs where the LBRs are already disabled.
*/
static void __intel_pmu_disable_all(void)
{ {
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
...@@ -1256,15 +1259,20 @@ static void intel_pmu_disable_all(void) ...@@ -1256,15 +1259,20 @@ static void intel_pmu_disable_all(void)
intel_bts_disable_local(); intel_bts_disable_local();
intel_pmu_pebs_disable_all(); intel_pmu_pebs_disable_all();
}
static void intel_pmu_disable_all(void)
{
__intel_pmu_disable_all();
intel_pmu_lbr_disable_all(); intel_pmu_lbr_disable_all();
} }
static void intel_pmu_enable_all(int added) static void __intel_pmu_enable_all(int added, bool pmi)
{ {
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
intel_pmu_pebs_enable_all(); intel_pmu_pebs_enable_all();
intel_pmu_lbr_enable_all(); intel_pmu_lbr_enable_all(pmi);
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
...@@ -1280,6 +1288,11 @@ static void intel_pmu_enable_all(int added) ...@@ -1280,6 +1288,11 @@ static void intel_pmu_enable_all(int added)
intel_bts_enable_local(); intel_bts_enable_local();
} }
static void intel_pmu_enable_all(int added)
{
__intel_pmu_enable_all(added, false);
}
/* /*
* Workaround for: * Workaround for:
* Intel Errata AAK100 (model 26) * Intel Errata AAK100 (model 26)
...@@ -1573,7 +1586,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) ...@@ -1573,7 +1586,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
*/ */
if (!x86_pmu.late_ack) if (!x86_pmu.late_ack)
apic_write(APIC_LVTPC, APIC_DM_NMI); apic_write(APIC_LVTPC, APIC_DM_NMI);
intel_pmu_disable_all(); __intel_pmu_disable_all();
handled = intel_pmu_drain_bts_buffer(); handled = intel_pmu_drain_bts_buffer();
handled += intel_bts_interrupt(); handled += intel_bts_interrupt();
status = intel_pmu_get_status(); status = intel_pmu_get_status();
...@@ -1658,7 +1671,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) ...@@ -1658,7 +1671,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
goto again; goto again;
done: done:
intel_pmu_enable_all(0); __intel_pmu_enable_all(0, true);
/* /*
* Only unmask the NMI after the overflow counters * Only unmask the NMI after the overflow counters
* have been reset. This avoids spurious NMIs on * have been reset. This avoids spurious NMIs on
......
...@@ -132,12 +132,16 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); ...@@ -132,12 +132,16 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
* otherwise it becomes near impossible to get a reliable stack. * otherwise it becomes near impossible to get a reliable stack.
*/ */
static void __intel_pmu_lbr_enable(void) static void __intel_pmu_lbr_enable(bool pmi)
{ {
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
u64 debugctl, lbr_select = 0; u64 debugctl, lbr_select = 0;
if (cpuc->lbr_sel) { /*
* No need to reprogram LBR_SELECT in a PMI, as it
* did not change.
*/
if (cpuc->lbr_sel && !pmi) {
lbr_select = cpuc->lbr_sel->config; lbr_select = cpuc->lbr_sel->config;
wrmsrl(MSR_LBR_SELECT, lbr_select); wrmsrl(MSR_LBR_SELECT, lbr_select);
} }
...@@ -351,12 +355,12 @@ void intel_pmu_lbr_disable(struct perf_event *event) ...@@ -351,12 +355,12 @@ void intel_pmu_lbr_disable(struct perf_event *event)
} }
} }
void intel_pmu_lbr_enable_all(void) void intel_pmu_lbr_enable_all(bool pmi)
{ {
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
if (cpuc->lbr_users) if (cpuc->lbr_users)
__intel_pmu_lbr_enable(); __intel_pmu_lbr_enable(pmi);
} }
void intel_pmu_lbr_disable_all(void) void intel_pmu_lbr_disable_all(void)
......
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