Commit 1b3b27b2 authored by tianci yin's avatar tianci yin Committed by Alex Deucher

drm/amd/powerplay: improve OD code robustness

add protection code to avoid lower frequency trigger over drive.
Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarTianci Yin <tianci.yin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4944af67
...@@ -3589,8 +3589,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons ...@@ -3589,8 +3589,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
} }
if (i >= sclk_table->count) { if (i >= sclk_table->count) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; if (sclk > sclk_table->dpm_levels[i-1].value) {
sclk_table->dpm_levels[i-1].value = sclk; data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
sclk_table->dpm_levels[i-1].value = sclk;
}
} else { } else {
/* TODO: Check SCLK in DAL's minimum clocks /* TODO: Check SCLK in DAL's minimum clocks
* in case DeepSleep divider update is required. * in case DeepSleep divider update is required.
...@@ -3607,8 +3609,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons ...@@ -3607,8 +3609,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
} }
if (i >= mclk_table->count) { if (i >= mclk_table->count) {
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; if (mclk > mclk_table->dpm_levels[i-1].value) {
mclk_table->dpm_levels[i-1].value = mclk; data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
mclk_table->dpm_levels[i-1].value = mclk;
}
} }
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
......
...@@ -3266,8 +3266,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co ...@@ -3266,8 +3266,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
} }
if (i >= sclk_table->count) { if (i >= sclk_table->count) {
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; if (sclk > sclk_table->dpm_levels[i-1].value) {
sclk_table->dpm_levels[i-1].value = sclk; data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
sclk_table->dpm_levels[i-1].value = sclk;
}
} }
for (i = 0; i < mclk_table->count; i++) { for (i = 0; i < mclk_table->count; i++) {
...@@ -3276,8 +3278,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co ...@@ -3276,8 +3278,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
} }
if (i >= mclk_table->count) { if (i >= mclk_table->count) {
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; if (mclk > mclk_table->dpm_levels[i-1].value) {
mclk_table->dpm_levels[i-1].value = mclk; data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
mclk_table->dpm_levels[i-1].value = mclk;
}
} }
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
......
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