Commit 1baa496d authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Luis Henriques

ARM: dts: tegra20: fix GR3D, DSI unit and reg base addresses

commit de47699d upstream.

Commit 58ecb23f ("ARM: tegra: add missing unit addresses to DT") added
unit address and changed reg base for GR3D and DSI host1x modules, but these
addresses belongs to GR2D and TVO modules respectively. Fix it by changing
modules unit and reg base addresses to proper ones.
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Fixes: 58ecb23f (ARM: tegra: add missing unit addresses to DT)
Reviewed-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarLuis Henriques <luis.henriques@canonical.com>
parent 00b9f78e
......@@ -76,9 +76,9 @@ gr2d@54140000 {
reset-names = "2d";
};
gr3d@54140000 {
gr3d@54180000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54140000 0x00040000>;
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
......@@ -138,9 +138,9 @@ tvo@542c0000 {
status = "disabled";
};
dsi@542c0000 {
dsi@54300000 {
compatible = "nvidia,tegra20-dsi";
reg = <0x542c0000 0x00040000>;
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_DSI>;
resets = <&tegra_car 48>;
reset-names = "dsi";
......
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