Commit 1d158315 authored by Brian Norris's avatar Brian Norris

doc: dt: mtd: stop referring to driver code for spi-nor IDs

Pull the supported chip names from drivers/mtd/devices/m25p80.c and stop
pointing readers to Linux code.

Also (although I see this habit repeated throughout the
Documentation/devicetree/bindings/ tree), stop using the title "driver"
in this file, when we're trying explicitly to describe hardware, not
software.
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Cc: <devicetree@vger.kernel.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
parent c1711b29
* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
* SPI NOR flash: ST M25Pxx (and similar) serial flash chips
Required properties:
- #address-cells, #size-cells : Must be present if the device has sub-nodes
representing partitions.
- compatible : May include a device-specific string consisting of the
manufacturer and name of the chip. Bear in mind the DT binding
is not Linux-only, but in case of Linux, see the "m25p_ids"
table in drivers/mtd/devices/m25p80.c for the list of supported
chips.
manufacturer and name of the chip. A list of supported chip
names follows.
Must also include "jedec,spi-nor" for any SPI NOR flash that can
be identified by the JEDEC READ ID opcode (0x9F).
Supported chip names:
at25df321a
at25df641
at26df081a
mr25h256
mx25l4005a
mx25l1606e
mx25l6405d
mx25l12805d
mx25l25635e
n25q064
n25q128a11
n25q128a13
n25q512a
s25fl256s1
s25fl512s
s25sl12801
s25fl008k
s25fl064k
sst25vf040b
m25p40
m25p80
m25p16
m25p32
m25p64
m25p128
w25x80
w25x32
w25q32
w25q32dw
w25q80bl
w25q128
w25q256
The following chip names have been used historically to
designate quirky versions of flash chips that do not support the
JEDEC READ ID opcode (0x9F):
m25p05-nonjedec
m25p10-nonjedec
m25p20-nonjedec
m25p40-nonjedec
m25p80-nonjedec
m25p16-nonjedec
m25p32-nonjedec
m25p64-nonjedec
m25p128-nonjedec
- reg : Chip-Select number
- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
......
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