Commit 1e6c9c28 authored by Andrew Victor's avatar Andrew Victor Committed by Russell King

[ARM] 3242/2: AT91RM9200 support for 2.6 (Serial)

Patch from Andrew Victor

This patch adds support to the 2.6 kernel series for the Atmel
AT91RM9200 processor.

This patch is the Serial driver.

This version uses the newly re-written GPL'ed hardware headers.
Signed-off-by: default avatarAndrew Victor <andrew@sanpeople.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 97712717
......@@ -280,6 +280,40 @@ config SERIAL_AMBA_PL011_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
config SERIAL_AT91
bool "AT91RM9200 serial port support"
depends on ARM && ARCH_AT91RM9200
select SERIAL_CORE
help
This enables the driver for the on-chip UARTs of the AT91RM9200
processor.
config SERIAL_AT91_CONSOLE
bool "Support for console on AT91RM9200 serial port"
depends on SERIAL_AT91=y
select SERIAL_CORE_CONSOLE
help
Say Y here if you wish to use a UART on the AT91RM9200 as the system
console (the system console is the device which receives all kernel
messages and warnings and which allows logins in single user mode).
config SERIAL_AT91_TTYAT
bool "Install as device ttyAT0-4 instead of ttyS0-4"
depends on SERIAL_AT91=y
help
Say Y here if you wish to have the five internal AT91RM9200 UARTs
appear as /dev/ttyAT0-4 (major 240, minor 0-4) instead of the
normal /dev/ttyS0-4 (major 4, minor 64-68). This is necessary if
you also want other UARTs, such as external 8250/16C550 compatible
UARTs.
The ttySn nodes are legally reserved for the 8250 serial driver
but are often misused by other serial drivers.
To use this, you should create suitable ttyATn device nodes in
/dev/, and pass "console=ttyATn" to the kernel.
Say Y if you have an external 8250/16C550 UART. If unsure, say N.
config SERIAL_CLPS711X
tristate "CLPS711X serial port support"
depends on ARM && ARCH_CLPS711X
......
......@@ -56,3 +56,4 @@ obj-$(CONFIG_SERIAL_JSM) += jsm/
obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o
obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o
obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
obj-$(CONFIG_SERIAL_AT91) += at91_serial.o
This diff is collapsed.
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Peripheral Data Controller (PDC) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_PDC_H
#define AT91RM9200_PDC_H
#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
#endif
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* USART registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_USART_H
#define AT91RM9200_USART_H
#define AT91_US_CR 0x00 /* Control Register */
#define AT91_US_RSTRX (1 << 2) /* Reset Receiver */
#define AT91_US_RSTTX (1 << 3) /* Reset Transmitter */
#define AT91_US_RXEN (1 << 4) /* Receiver Enable */
#define AT91_US_RXDIS (1 << 5) /* Receiver Disable */
#define AT91_US_TXEN (1 << 6) /* Transmitter Enable */
#define AT91_US_TXDIS (1 << 7) /* Transmitter Disable */
#define AT91_US_RSTSTA (1 << 8) /* Reset Status Bits */
#define AT91_US_STTBRK (1 << 9) /* Start Break */
#define AT91_US_STPBRK (1 << 10) /* Stop Break */
#define AT91_US_STTTO (1 << 11) /* Start Time-out */
#define AT91_US_SENDA (1 << 12) /* Send Address */
#define AT91_US_RSTIT (1 << 13) /* Reset Iterations */
#define AT91_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
#define AT91_US_RETTO (1 << 15) /* Rearm Time-out */
#define AT91_US_DTREN (1 << 16) /* Data Terminal Ready Enable */
#define AT91_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable */
#define AT91_US_RTSEN (1 << 18) /* Request To Send Enable */
#define AT91_US_RTSDIS (1 << 19) /* Request To Send Disable */
#define AT91_US_MR 0x04 /* Mode Register */
#define AT91_US_USMODE (0xf << 0) /* Mode of the USART */
#define AT91_US_USMODE_NORMAL 0
#define AT91_US_USMODE_RS485 1
#define AT91_US_USMODE_HWHS 2
#define AT91_US_USMODE_MODEM 3
#define AT91_US_USMODE_ISO7816_T0 4
#define AT91_US_USMODE_ISO7816_T1 6
#define AT91_US_USMODE_IRDA 8
#define AT91_US_USCLKS (3 << 4) /* Clock Selection */
#define AT91_US_CHRL (3 << 6) /* Character Length */
#define AT91_US_CHRL_5 (0 << 6)
#define AT91_US_CHRL_6 (1 << 6)
#define AT91_US_CHRL_7 (2 << 6)
#define AT91_US_CHRL_8 (3 << 6)
#define AT91_US_SYNC (1 << 8) /* Synchronous Mode Select */
#define AT91_US_PAR (7 << 9) /* Parity Type */
#define AT91_US_PAR_EVEN (0 << 9)
#define AT91_US_PAR_ODD (1 << 9)
#define AT91_US_PAR_SPACE (2 << 9)
#define AT91_US_PAR_MARK (3 << 9)
#define AT91_US_PAR_NONE (4 << 9)
#define AT91_US_PAR_MULTI_DROP (6 << 9)
#define AT91_US_NBSTOP (3 << 12) /* Number of Stop Bits */
#define AT91_US_NBSTOP_1 (0 << 12)
#define AT91_US_NBSTOP_1_5 (1 << 12)
#define AT91_US_NBSTOP_2 (2 << 12)
#define AT91_US_CHMODE (3 << 14) /* Channel Mode */
#define AT91_US_CHMODE_NORMAL (0 << 14)
#define AT91_US_CHMODE_ECHO (1 << 14)
#define AT91_US_CHMODE_LOC_LOOP (2 << 14)
#define AT91_US_CHMODE_REM_LOOP (3 << 14)
#define AT91_US_MSBF (1 << 16) /* Bit Order */
#define AT91_US_MODE9 (1 << 17) /* 9-bit Character Length */
#define AT91_US_CLKO (1 << 18) /* Clock Output Select */
#define AT91_US_OVER (1 << 19) /* Oversampling Mode */
#define AT91_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
#define AT91_US_DSNACK (1 << 21) /* Disable Successive NACK */
#define AT91_US_MAX_ITER (7 << 24) /* Max Iterations */
#define AT91_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
#define AT91_US_IER 0x08 /* Interrupt Enable Register */
#define AT91_US_RXRDY (1 << 0) /* Receiver Ready */
#define AT91_US_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_US_RXBRK (1 << 2) /* Break Received / End of Break */
#define AT91_US_ENDRX (1 << 3) /* End of Receiver Transfer */
#define AT91_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
#define AT91_US_OVRE (1 << 5) /* Overrun Error */
#define AT91_US_FRAME (1 << 6) /* Framing Error */
#define AT91_US_PARE (1 << 7) /* Parity Error */
#define AT91_US_TIMEOUT (1 << 8) /* Receiver Time-out */
#define AT91_US_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
#define AT91_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
#define AT91_US_RXBUFF (1 << 12) /* Reception Buffer Full */
#define AT91_US_NACK (1 << 13) /* Non Acknowledge */
#define AT91_US_RIIC (1 << 16) /* Ring Indicator Input Change */
#define AT91_US_DSRIC (1 << 17) /* Data Set Ready Input Change */
#define AT91_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change */
#define AT91_US_CTSIC (1 << 19) /* Clear to Send Input Change */
#define AT91_US_RI (1 << 20) /* RI */
#define AT91_US_DSR (1 << 21) /* DSR */
#define AT91_US_DCD (1 << 22) /* DCD */
#define AT91_US_CTS (1 << 23) /* CTS */
#define AT91_US_IDR 0x0c /* Interrupt Disable Register */
#define AT91_US_IMR 0x10 /* Interrupt Mask Register */
#define AT91_US_CSR 0x14 /* Channel Status Register */
#define AT91_US_RHR 0x18 /* Receiver Holding Register */
#define AT91_US_THR 0x1c /* Transmitter Holding Register */
#define AT91_US_BRGR 0x20 /* Baud Rate Generator Register */
#define AT91_US_CD (0xffff << 0) /* Clock Divider */
#define AT91_US_RTOR 0x24 /* Receiver Time-out Register */
#define AT91_US_TO (0xffff << 0) /* Time-out Value */
#define AT91_US_TTGR 0x28 /* Transmitter Timeguard Register */
#define AT91_US_TG (0xff << 0) /* Timeguard Value */
#define AT91_US_FIDI 0x40 /* FI DI Ratio Register */
#define AT91_US_NER 0x44 /* Number of Errors Register */
#define AT91_US_IF 0x4c /* IrDA Filter Register */
#endif
/*
* linux/include/asm-arm/mach/serial_at91rm9200.h
*
* Based on serial_sa1100.h by Nicolas Pitre
*
* Copyright (C) 2002 ATMEL Rousset
*
* Low level machine dependent UART functions.
*/
#include <linux/config.h>
struct uart_port;
/*
* This is a temporary structure for registering these
* functions; it is intended to be discarded after boot.
*/
struct at91rm9200_port_fns {
void (*set_mctrl)(struct uart_port *, u_int);
u_int (*get_mctrl)(struct uart_port *);
void (*enable_ms)(struct uart_port *);
void (*pm)(struct uart_port *, u_int, u_int);
int (*set_wake)(struct uart_port *, u_int);
int (*open)(struct uart_port *);
void (*close)(struct uart_port *);
};
#if defined(CONFIG_SERIAL_AT91)
void at91_register_uart_fns(struct at91rm9200_port_fns *fns);
void at91_register_uart(int idx, int port);
#else
#define at91_register_uart_fns(fns) do { } while (0)
#define at91_register_uart(idx,port) do { } while (0)
#endif
......@@ -67,6 +67,9 @@
/* Parisc type numbers. */
#define PORT_MUX 48
/* Atmel AT91RM9200 SoC */
#define PORT_AT91RM9200 49
/* Macintosh Zilog type numbers */
#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
#define PORT_PMAC_ZILOG 51
......
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