Commit 1f3a2c6e authored by James Hogan's avatar James Hogan Committed by Ralf Baechle

MIPS: MSA: Fix big-endian FPR_IDX implementation

The maximum word size is 64-bits since MSA state is saved using st.d
which stores two 64-bit words, therefore reimplement FPR_IDX using xor,
and only within each 64-bit word.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9169/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 466aec5f
...@@ -105,7 +105,7 @@ union fpureg { ...@@ -105,7 +105,7 @@ union fpureg {
#ifdef CONFIG_CPU_LITTLE_ENDIAN #ifdef CONFIG_CPU_LITTLE_ENDIAN
# define FPR_IDX(width, idx) (idx) # define FPR_IDX(width, idx) (idx)
#else #else
# define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx)) # define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
#endif #endif
#define BUILD_FPR_ACCESS(width) \ #define BUILD_FPR_ACCESS(width) \
......
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