drm/amdgpu: Query correct register for DF hashing on Aldebaran

For Aldebaran, driver needs to query DramMegaBaseAddress to
check if DF hashing is enabled.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

@@ -277,13 +277,14 @@ static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
 {
 	u32 tmp;
 
-	tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
-	if (adev->asic_type == CHIP_ALDEBARAN)
+	if (adev->asic_type == CHIP_ALDEBARAN) {
+		tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);
 		tmp &=
 		ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
-	else
+	} else {
+		tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
 		tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
-
+	}
 	tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 
 	return tmp;

drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h

@@ -33,6 +33,9 @@
 #define mmDF_CS_UMC_AON0_DramBaseAddress0								0x0044
 #define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX							0
 
+#define mmDF_GCM_AON0_DramMegaBaseAddress0								0x0064
+#define mmDF_GCM_AON0_DramMegaBaseAddress0_BASE_IDX							0
+
 #define smnPerfMonCtlLo0					0x01d440UL
 #define smnPerfMonCtlHi0					0x01d444UL
 #define smnPerfMonCtlLo1					0x01d450UL