Commit 1ff42c32 authored by Sebastian Andrzej Siewior's avatar Sebastian Andrzej Siewior Committed by Thomas Gleixner

x86: ce4100: Configure IOAPIC pins for USB and SATA to level type

The USB and SATA ioapic interrrupt pins are configured as edge type,
but need to be level type interrupts to work correctly.

[ tglx: Split out from the combo patch ]

Cc: Torben Hohn <torbenh@linutronix.de>
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Link: http://lkml.kernel.org/r/%3C20110427143052.GA15211%40linutronix.de%3ESigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 20443598
...@@ -347,7 +347,7 @@ usb@d,0 { ...@@ -347,7 +347,7 @@ usb@d,0 {
"pciclass0c03"; "pciclass0c03";
reg = <0x16800 0x0 0x0 0x0 0x0>; reg = <0x16800 0x0 0x0 0x0 0x0>;
interrupts = <22 3>; interrupts = <22 1>;
}; };
usb@d,1 { usb@d,1 {
...@@ -357,7 +357,7 @@ usb@d,1 { ...@@ -357,7 +357,7 @@ usb@d,1 {
"pciclass0c03"; "pciclass0c03";
reg = <0x16900 0x0 0x0 0x0 0x0>; reg = <0x16900 0x0 0x0 0x0 0x0>;
interrupts = <22 3>; interrupts = <22 1>;
}; };
sata@e,0 { sata@e,0 {
...@@ -367,7 +367,7 @@ sata@e,0 { ...@@ -367,7 +367,7 @@ sata@e,0 {
"pciclass0106"; "pciclass0106";
reg = <0x17000 0x0 0x0 0x0 0x0>; reg = <0x17000 0x0 0x0 0x0 0x0>;
interrupts = <23 3>; interrupts = <23 1>;
}; };
flash@f,0 { flash@f,0 {
......
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