Commit 20373e0c authored by Dinh Nguyen's avatar Dinh Nguyen

ARM: dts: socfpga: add timer resets for SoCFPGA platform

Add the resets property for all the timers on the Cyclone5/Arria5/Arria10
platforms.
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent cbbc488e
......@@ -849,6 +849,8 @@ timer0: timer0@ffc08000 {
reg = <0xffc08000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
resets = <&rst SPTIMER0_RESET>;
reset-names = "timer";
};
timer1: timer1@ffc09000 {
......@@ -857,6 +859,8 @@ timer1: timer1@ffc09000 {
reg = <0xffc09000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
resets = <&rst SPTIMER1_RESET>;
reset-names = "timer";
};
timer2: timer2@ffd00000 {
......@@ -865,6 +869,8 @@ timer2: timer2@ffd00000 {
reg = <0xffd00000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
resets = <&rst OSC1TIMER0_RESET>;
reset-names = "timer";
};
timer3: timer3@ffd01000 {
......@@ -873,6 +879,8 @@ timer3: timer3@ffd01000 {
reg = <0xffd01000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
resets = <&rst OSC1TIMER1_RESET>;
reset-names = "timer";
};
uart0: serial0@ffc02000 {
......
......@@ -786,6 +786,8 @@ timer0: timer0@ffc02700 {
reg = <0xffc02700 0x100>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
resets = <&rst SPTIMER0_RESET>;
reset-names = "timer";
};
timer1: timer1@ffc02800 {
......@@ -794,6 +796,8 @@ timer1: timer1@ffc02800 {
reg = <0xffc02800 0x100>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
resets = <&rst SPTIMER1_RESET>;
reset-names = "timer";
};
timer2: timer2@ffd00000 {
......@@ -802,6 +806,8 @@ timer2: timer2@ffd00000 {
reg = <0xffd00000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
resets = <&rst L4SYSTIMER0_RESET>;
reset-names = "timer";
};
timer3: timer3@ffd00100 {
......@@ -810,6 +816,8 @@ timer3: timer3@ffd00100 {
reg = <0xffd01000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
resets = <&rst L4SYSTIMER1_RESET>;
reset-names = "timer";
};
uart0: serial0@ffc02000 {
......
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