Commit 2078e1e7 authored by Keith Busch's avatar Keith Busch Committed by Bjorn Helgaas

PCI/LINK: Add Kconfig option (default off)

e8303bb7 ("PCI/LINK: Report degraded links via link bandwidth
notification") added dmesg logging whenever a link changes speed or width
to a state that is considered degraded.  Unfortunately, it cannot
differentiate signal integrity-related link changes from those
intentionally initiated by an endpoint driver, including drivers that may
live in userspace or VMs when making use of vfio-pci.  Some GPU drivers
actively manage the link state to save power, which generates a stream of
messages like this:

  vfio-pci 0000:07:00.0: 32.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x16 link at 0000:00:02.0 (capable of 64.000 Gb/s with 5 GT/s x16 link)

Since we can't distinguish the intentional changes from the signal
integrity issues, leave the reporting turned off by default.  Add a Kconfig
option to turn it on if desired.

Fixes: e8303bb7 ("PCI/LINK: Report degraded links via link bandwidth notification")
Link: https://lore.kernel.org/linux-pci/20190501142942.26972-1-keith.busch@intel.comSigned-off-by: default avatarKeith Busch <keith.busch@intel.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 15d2aba7
...@@ -142,3 +142,11 @@ config PCIE_PTM ...@@ -142,3 +142,11 @@ config PCIE_PTM
This is only useful if you have devices that support PTM, but it This is only useful if you have devices that support PTM, but it
is safe to enable even if you don't. is safe to enable even if you don't.
config PCIE_BW
bool "PCI Express Bandwidth Change Notification"
depends on PCIEPORTBUS
help
This enables PCI Express Bandwidth Change Notification. If
you know link width or rate changes occur only to correct
unreliable links, you may answer Y.
...@@ -3,7 +3,6 @@ ...@@ -3,7 +3,6 @@
# Makefile for PCI Express features and port driver # Makefile for PCI Express features and port driver
pcieportdrv-y := portdrv_core.o portdrv_pci.o err.o pcieportdrv-y := portdrv_core.o portdrv_pci.o err.o
pcieportdrv-y += bw_notification.o
obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
...@@ -13,3 +12,4 @@ obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o ...@@ -13,3 +12,4 @@ obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o
obj-$(CONFIG_PCIE_PME) += pme.o obj-$(CONFIG_PCIE_PME) += pme.o
obj-$(CONFIG_PCIE_DPC) += dpc.o obj-$(CONFIG_PCIE_DPC) += dpc.o
obj-$(CONFIG_PCIE_PTM) += ptm.o obj-$(CONFIG_PCIE_PTM) += ptm.o
obj-$(CONFIG_PCIE_BW) += bw_notification.o
...@@ -49,7 +49,11 @@ int pcie_dpc_init(void); ...@@ -49,7 +49,11 @@ int pcie_dpc_init(void);
static inline int pcie_dpc_init(void) { return 0; } static inline int pcie_dpc_init(void) { return 0; }
#endif #endif
#ifdef CONFIG_PCIE_BW
int pcie_bandwidth_notification_init(void); int pcie_bandwidth_notification_init(void);
#else
static inline int pcie_bandwidth_notification_init(void) { return 0; }
#endif
/* Port Type */ /* Port Type */
#define PCIE_ANY_PORT (~0) #define PCIE_ANY_PORT (~0)
......
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