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Commit 21604cdc authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC cleanups from Olof Johansson:
 "This branch contains code cleanups, moves and removals for 3.13.

  Qualcomm msm targets had a bunch of code removal for legacy non-DT
  platforms.  Nomadik saw more device tree conversions and cleanup of
  old code.  Tegra has some code refactoring, etc.

  One longish patch series from Sebastian Hasselbarth changes the
  init_time hooks and tries to use a generic implementation for most
  platforms, since they were all doing more or less the same things.

  Finally the "shark" platform is removed in this release.  It's been
  abandoned for a while and nobody seems to care enough to keep it
  around.  If someone comes along and wants to resurrect it, the removal
  can easily be reverted and code brought back.

  Beyond this, mostly a bunch of removals of stale content across the
  board, etc"

* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (79 commits)
  ARM: gemini: convert to GENERIC_CLOCKEVENTS
  ARM: EXYNOS: remove CONFIG_MACH_EXYNOS[4, 5]_DT config options
  ARM: OMAP3: control: add API for setting IVA bootmode
  ARM: OMAP3: CM/control: move CM scratchpad save to CM driver
  ARM: OMAP3: McBSP: do not access CM register directly
  ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock
  ARM: OMAP2: CM/PM: remove direct register accesses outside CM code
  MAINTAINERS: Add patterns for DTS files for AT91
  ARM: at91: remove init_machine() as default is suitable
  ARM: at91/dt: split sama5d3 peripheral definitions
  ARM: at91/dt: split sam9x5 peripheral definitions
  ARM: Remove temporary sched_clock.h header
  ARM: clps711x: Use linux/sched_clock.h
  MAINTAINERS: Add DTS files to patterns for Samsung platform
  ARM: EXYNOS: remove unnecessary header inclusions from exynos4/5 dt machine file
  ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
  clk: nomadik: fix missing __init on nomadik_src_init
  ARM: drop explicit selection of HAVE_CLK and CLKDEV_LOOKUP
  ARM: S3C64XX: Kill CONFIG_PLAT_S3C64XX
  ASoC: samsung: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
  ...
parents beb5bfe4 f3372c01
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MAINTAINERS
View file @ 21604cdc
......@@ -763,6 +763,10 @@ W: http://maxim.org.za/at91_26.html
W: http://www.linux4sam.org
S: Supported
F: arch/arm/mach-at91/
F: arch/arm/boot/dts/at91*.dts
F: arch/arm/boot/dts/at91*.dtsi
F: arch/arm/boot/dts/sama*.dts
F: arch/arm/boot/dts/sama*.dtsi
ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <rob.herring@calxeda.com>
......@@ -1157,11 +1161,6 @@ S: Maintained
F: arch/arm/mach-rockchip/
F: drivers/*/*rockchip*
ARM/SHARK MACHINE SUPPORT
M: Alexander Schulz <alex@shark-linux.de>
W: http://www.shark-linux.de/shark.html
S: Maintained
ARM/SAMSUNG ARM ARCHITECTURES
M: Ben Dooks <ben-linux@fluff.org>
M: Kukjin Kim <kgene.kim@samsung.com>
......@@ -1169,6 +1168,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
W: http://www.fluff.org/ben/linux/
S: Maintained
F: arch/arm/boot/dts/s3c*
F: arch/arm/boot/dts/exynos*
F: arch/arm/plat-samsung/
F: arch/arm/mach-s3c24*/
F: arch/arm/mach-s3c64xx/
......
arch/arm/Kconfig
View file @ 21604cdc
......@@ -358,7 +358,6 @@ config ARCH_AT91
bool "Atmel AT91"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select HAVE_CLK
select IRQ_DOMAIN
select NEED_MACH_GPIO_H
select NEED_MACH_IO_H if PCCARD
......@@ -372,7 +371,6 @@ config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
select CPU_ARM720T
......@@ -386,8 +384,9 @@ config ARCH_CLPS711X
config ARCH_GEMINI
bool "Cortina Systems Gemini"
select ARCH_REQUIRE_GPIOLIB
select ARCH_USES_GETTIMEOFFSET
select CLKSRC_MMIO
select CPU_FA526
select GENERIC_CLOCKEVENTS
select NEED_MACH_GPIO_H
help
Support for the Cortina Systems Gemini family SoCs
......@@ -631,7 +630,6 @@ config ARCH_PXA
config ARCH_MSM
bool "Qualcomm MSM"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_OF if OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
......@@ -649,7 +647,6 @@ config ARCH_SHMOBILE
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_CLK
select HAVE_MACH_CLKDEV
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
......@@ -706,7 +703,6 @@ config ARCH_S3C24XX
select CLKSRC_SAMSUNG_PWM
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
......@@ -730,18 +726,19 @@ config ARCH_S3C64XX
select CPU_V6
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_TCM
select NEED_MACH_GPIO_H
select NO_IOPORT
select PLAT_SAMSUNG
select PM_GENERIC_DOMAINS
select S3C_DEV_NAND
select S3C_GPIO_TRACK
select SAMSUNG_ATAGS
select SAMSUNG_CLKSRC
select SAMSUNG_GPIOLIB_4BIT
select SAMSUNG_WAKEMASK
select SAMSUNG_WDT_RESET
select USB_ARCH_HAS_OHCI
help
......@@ -754,7 +751,6 @@ config ARCH_S5P64X0
select CPU_V6
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
......@@ -773,7 +769,6 @@ config ARCH_S5PC100
select CPU_V7
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
......@@ -793,7 +788,6 @@ config ARCH_S5PV210
select CPU_V7
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
......@@ -810,11 +804,9 @@ config ARCH_EXYNOS
select ARCH_REQUIRE_GPIOLIB
select ARCH_SPARSEMEM_ENABLE
select ARM_GIC
select CLKDEV_LOOKUP
select COMMON_CLK
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
......@@ -824,20 +816,6 @@ config ARCH_EXYNOS
help
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
config ARCH_SHARK
bool "Shark"
select ARCH_USES_GETTIMEOFFSET
select CPU_SA110
select ISA
select ISA_DMA
select NEED_MACH_MEMORY_H
select PCI
select VIRT_TO_BUS
select ZONE_DMA
help
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
......@@ -865,7 +843,6 @@ config ARCH_OMAP1
select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select HAVE_CLK
select HAVE_IDE
select IRQ_DOMAIN
select NEED_MACH_IO_H if PCCARD
......@@ -1009,9 +986,7 @@ source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-s3c24xx/Kconfig"
if ARCH_S3C64XX
source "arch/arm/mach-s3c64xx/Kconfig"
endif
source "arch/arm/mach-s5p64x0/Kconfig"
......@@ -1431,12 +1406,6 @@ config PCI_NANOENGINE
config PCI_SYSCALL
def_bool PCI
# Select the host bridge type
config PCI_HOST_VIA82C505
bool
depends on PCI && ARCH_SHARK
default y
config PCI_HOST_ITE8152
bool
depends on PCI && MACH_ARMCORE
......
arch/arm/Makefile
View file @ 21604cdc
......@@ -188,7 +188,6 @@ machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0
machine-$(CONFIG_ARCH_S5PC100) += s5pc100
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_SHARK) += shark
machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile
machine-$(CONFIG_ARCH_SIRF) += prima2
......
arch/arm/boot/compressed/Makefile
View file @ 21604cdc
......@@ -44,10 +44,6 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
OBJS += ll_char_wr.o font.o
endif
ifeq ($(CONFIG_ARCH_SHARK),y)
OBJS += head-shark.o ofw-shark.o
endif
ifeq ($(CONFIG_ARCH_SA1100),y)
OBJS += head-sa1100.o
endif
......
arch/arm/boot/compressed/head-shark.S deleted 100644 → 0
View file @ beb5bfe4
/* The head-file for the Shark
* by Alexander Schulz
*
* Does the following:
* - get the memory layout from firmware. This can only be done as long as the mmu
* is still on.
* - switch the mmu off, so we have physical addresses
* - copy the kernel to 0x08508000. This is done to have a fixed address where the
* C-parts (misc.c) are executed. This address must be known at compile-time,
* but the load-address of the kernel depends on how much memory is installed.
* - Jump to this location.
* - Set r8 with 0, r7 with the architecture ID for head.S
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.section ".start", "ax"
.arch armv4
b __beginning
__ofw_data: .long 0 @ the number of memory blocks
.space 128 @ (startaddr,size) ...
.space 128 @ bootargs
.align
__beginning: mov r4, r0 @ save the entry to the firmware
mov r0, #0xC0 @ disable irq and fiq
mov r1, r0
mrs r3, cpsr
bic r2, r3, r0
eor r2, r2, r1
msr cpsr_c, r2
mov r0, r4 @ get the Memory layout from firmware
adr r1, __ofw_data
add r2, r1, #4
mov lr, pc
b ofw_init
mov r1, #0
adr r2, __mmu_off @ calculate physical address
sub r2, r2, #0xf0000000 @ openprom maps us at f000 virt, 0e50 phys
adr r0, __ofw_data
ldr r0, [r0, #4]
add r2, r2, r0
add r2, r2, #0x00500000
mrc p15, 0, r3, c1, c0
bic r3, r3, #0xC @ Write Buffer and DCache
bic r3, r3, #0x1000 @ ICache
mcr p15, 0, r3, c1, c0 @ disabled
mov r0, #0
mcr p15, 0, r0, c7, c7 @ flush I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
mcr p15, 0, r0, c8, c7 @ flush I,D TLBs on v4
bic r3, r3, #0x1 @ MMU
mcr p15, 0, r3, c1, c0 @ disabled
mov pc, r2
__copy_target: .long 0x08507FFC
__copy_end: .long 0x08607FFC
.word _start
.word __bss_start
.align
__temp_stack: .space 128
__mmu_off:
adr r0, __ofw_data @ read the 1. entry of the memory map
ldr r0, [r0, #4]
orr r0, r0, #0x00600000
sub r0, r0, #4
ldr r1, __copy_end
ldr r3, __copy_target
/* r0 = 0x0e600000 (current end of kernelcode)
* r3 = 0x08508000 (where it should begin)
* r1 = 0x08608000 (end of copying area, 1MB)
* The kernel is compressed, so 1 MB should be enough.
* copy the kernel to the beginning of physical memory
* We start from the highest address, so we can copy
* from 0x08500000 to 0x08508000 if we have only 8MB
*/
/* As we get more 2.6-kernels it gets more and more
* uncomfortable to be bound to kernel images of 1MB only.
* So we add a loop here, to be able to copy some more.
* Alexander Schulz 2005-07-17
*/
mov r4, #3 @ How many megabytes to copy
__MoveCode: sub r4, r4, #1
__Copy: ldr r2, [r0], #-4
str r2, [r1], #-4
teq r1, r3
bne __Copy
/* The firmware maps us in blocks of 1 MB, the next block is
_below_ the last one. So our decrementing source pointer
ist right here, but the destination pointer must be increased
by 2 MB */
add r1, r1, #0x00200000
add r3, r3, #0x00100000
teq r4, #0
bne __MoveCode
/* and jump to it */
adr r2, __go_on @ where we want to jump
adr r0, __ofw_data @ read the 1. entry of the memory map
ldr r0, [r0, #4]
sub r2, r2, r0 @ we are mapped add 0e50 now, sub that (-0e00)
sub r2, r2, #0x00500000 @ -0050
ldr r0, __copy_target @ and add 0850 8000 instead
add r0, r0, #4
add r2, r2, r0
mov pc, r2 @ and jump there
__go_on:
adr sp, __temp_stack
add sp, sp, #128
adr r0, __ofw_data
mov lr, pc
b create_params
mov r8, #0
mov r7, #15
arch/arm/boot/compressed/ofw-shark.c deleted 100644 → 0
View file @ beb5bfe4
/*
* linux/arch/arm/boot/compressed/ofw-shark.c
*
* by Alexander Schulz
*
* This file is used to get some basic information
* about the memory layout of the shark we are running
* on. Memory is usually divided in blocks a 8 MB.
* And bootargs are copied from OpenFirmware.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/setup.h>
#include <asm/page.h>
asmlinkage void
create_params (unsigned long *buffer)
{
/* Is there a better address? Also change in mach-shark/core.c */
struct tag *tag = (struct tag *) 0x08003000;
int j,i,m,k,nr_banks,size;
unsigned char *c;
k = 0;
/* Head of the taglist */
tag->hdr.tag = ATAG_CORE;
tag->hdr.size = tag_size(tag_core);
tag->u.core.flags = 1;
tag->u.core.pagesize = PAGE_SIZE;
tag->u.core.rootdev = 0;
/* Build up one tagged block for each memory region */
size=0;
nr_banks=(unsigned int) buffer[0];
for (j=0;j<nr_banks;j++){
/* search the lowest address and put it into the next entry */
/* not a fast sort algorithm, but there are at most 8 entries */
/* and this is used only once anyway */
m=0xffffffff;
for (i=0;i<(unsigned int) buffer[0];i++){
if (buffer[2*i+1]<m) {
m=buffer[2*i+1];
k=i;
}
}
tag = tag_next(tag);
tag->hdr.tag = ATAG_MEM;
tag->hdr.size = tag_size(tag_mem32);
tag->u.mem.size = buffer[2*k+2];
tag->u.mem.start = buffer[2*k+1];
size += buffer[2*k+2];
buffer[2*k+1]=0xffffffff; /* mark as copied */
}
/* The command line */
tag = tag_next(tag);
tag->hdr.tag = ATAG_CMDLINE;
c=(unsigned char *)(&buffer[34]);
j=0;
while (*c) tag->u.cmdline.cmdline[j++]=*c++;
tag->u.cmdline.cmdline[j]=0;
tag->hdr.size = (j + 7 + sizeof(struct tag_header)) >> 2;
/* Hardware revision */
tag = tag_next(tag);
tag->hdr.tag = ATAG_REVISION;
tag->hdr.size = tag_size(tag_revision);
tag->u.revision.rev = ((unsigned char) buffer[33])-'0';
/* End of the taglist */
tag = tag_next(tag);
tag->hdr.tag = 0;
tag->hdr.size = 0;
}
typedef int (*ofw_handle_t)(void *);
/* Everything below is called with a wrong MMU setting.
* This means: no string constants, no initialization of
* arrays, no global variables! This is ugly but I didn't
* want to write this in assembler :-)
*/
int
of_decode_int(const unsigned char *p)
{
unsigned int i = *p++ << 8;
i = (i + *p++) << 8;
i = (i + *p++) << 8;
return (i + *p);
}
int
OF_finddevice(ofw_handle_t openfirmware, char *name)
{
unsigned int args[8];
char service[12];
service[0]='f';
service[1]='i';
service[2]='n';
service[3]='d';
service[4]='d';
service[5]='e';
service[6]='v';
service[7]='i';
service[8]='c';
service[9]='e';
service[10]='\0';
args[0]=(unsigned int)service;
args[1]=1;
args[2]=1;
args[3]=(unsigned int)name;
if (openfirmware(args) == -1)
return -1;
return args[4];
}
int
OF_getproplen(ofw_handle_t openfirmware, int handle, char *prop)
{
unsigned int args[8];
char service[12];
service[0]='g';
service[1]='e';
service[2]='t';
service[3]='p';
service[4]='r';
service[5]='o';
service[6]='p';
service[7]='l';
service[8]='e';
service[9]='n';
service[10]='\0';
args[0] = (unsigned int)service;
args[1] = 2;
args[2] = 1;
args[3] = (unsigned int)handle;
args[4] = (unsigned int)prop;
if (openfirmware(args) == -1)
return -1;
return args[5];
}
int
OF_getprop(ofw_handle_t openfirmware, int handle, char *prop, void *buf, unsigned int buflen)
{
unsigned int args[8];
char service[8];
service[0]='g';
service[1]='e';
service[2]='t';
service[3]='p';
service[4]='r';
service[5]='o';
service[6]='p';
service[7]='\0';
args[0] = (unsigned int)service;
args[1] = 4;
args[2] = 1;
args[3] = (unsigned int)handle;
args[4] = (unsigned int)prop;
args[5] = (unsigned int)buf;
args[6] = buflen;
if (openfirmware(args) == -1)
return -1;
return args[7];
}
asmlinkage void ofw_init(ofw_handle_t o, int *nomr, int *pointer)
{
int phandle,i,mem_len,buffer[32];
char temp[15];
temp[0]='/';
temp[1]='m';
temp[2]='e';
temp[3]='m';
temp[4]='o';
temp[5]='r';
temp[6]='y';
temp[7]='\0';
phandle=OF_finddevice(o,temp);
temp[0]='r';
temp[1]='e';
temp[2]='g';
temp[3]='\0';
mem_len = OF_getproplen(o,phandle, temp);
OF_getprop(o,phandle, temp, buffer, mem_len);
*nomr=mem_len >> 3;
for (i=0; i<=mem_len/4; i++) pointer[i]=of_decode_int((const unsigned char *)&buffer[i]);
temp[0]='/';
temp[1]='c';
temp[2]='h';
temp[3]='o';
temp[4]='s';
temp[5]='e';
temp[6]='n';
temp[7]='\0';
phandle=OF_finddevice(o,temp);
temp[0]='b';
temp[1]='o';
temp[2]='o';
temp[3]='t';
temp[4]='a';
temp[5]='r';
temp[6]='g';
temp[7]='s';
temp[8]='\0';
mem_len = OF_getproplen(o,phandle, temp);
OF_getprop(o,phandle, temp, buffer, mem_len);
if (mem_len > 128) mem_len=128;
for (i=0; i<=mem_len/4; i++) pointer[i+33]=buffer[i];
pointer[i+33]=0;
temp[0]='/';
temp[1]='\0';
phandle=OF_finddevice(o,temp);
temp[0]='b';
temp[1]='a';
temp[2]='n';
temp[3]='n';
temp[4]='e';
temp[5]='r';
temp[6]='-';
temp[7]='n';
temp[8]='a';
temp[9]='m';
temp[10]='e';
temp[11]='\0';
mem_len = OF_getproplen(o,phandle, temp);
OF_getprop(o,phandle, temp, buffer, mem_len);
* ((unsigned char *) &pointer[32]) = ((unsigned char *) buffer)[mem_len-2];
}
arch/arm/boot/dts/Makefile
View file @ 21604cdc
......@@ -103,8 +103,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
kirkwood-ts219-6282.dtb \
kirkwood-openblocks_a6.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
......
arch/arm/boot/dts/at91sam9g25.dtsi
View file @ 21604cdc
......@@ -7,6 +7,8 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_usart3.dtsi"
#include "at91sam9x5_macb0.dtsi"
/ {
model = "Atmel AT91SAM9G25 SoC";
......
arch/arm/boot/dts/at91sam9g35.dtsi
View file @ 21604cdc
......@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_macb0.dtsi"
/ {
model = "Atmel AT91SAM9G35 SoC";
......
arch/arm/boot/dts/at91sam9x25.dtsi
View file @ 21604cdc
......@@ -7,6 +7,9 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_usart3.dtsi"
#include "at91sam9x5_macb0.dtsi"
#include "at91sam9x5_macb1.dtsi"
/ {
model = "Atmel AT91SAM9X25 SoC";
......@@ -22,27 +25,6 @@ pinctrl@fffff400 {
0x80000000 0xfffd0000 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
macb1 {
pinctrl_macb1_rmii: macb1_rmii-0 {
atmel,pins =
<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
};
};
};
macb1: ethernet@f8030000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
};
};
};
......
arch/arm/boot/dts/at91sam9x35.dtsi
View file @ 21604cdc
......@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
#include "at91sam9x5_macb0.dtsi"
/ {
model = "Atmel AT91SAM9X35 SoC";
......
arch/arm/boot/dts/at91sam9x5.dtsi
View file @ 21604cdc
......@@ -206,29 +206,6 @@ pinctrl_usart2_sck: usart2_sck-0 {
};
};
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
};
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
};
pinctrl_usart3_sck: usart3_sck-0 {
atmel,pins =
<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
};
};
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
......@@ -277,34 +254,6 @@ AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
};
};
mmc0 {
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
atmel,pins =
......@@ -610,22 +559,6 @@ usart2: serial@f8024000 {
status = "disabled";
};
macb0: ethernet@f802c000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "disabled";
};
macb1: ethernet@f8030000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
status = "disabled";
};
i2c0: i2c@f8010000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8010000 0x100>;
......
arch/arm/boot/dts/at91sam9x5_macb0.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
* Ethernet interface.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff400 {
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
};
};
};
macb0: ethernet@f802c000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/at91sam9x5_macb1.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
* Ethernet interfaces.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff400 {
macb1 {
pinctrl_macb1_rmii: macb1_rmii-0 {
atmel,pins =
<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
};
};
};
macb1: ethernet@f8030000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/at91sam9x5_usart3.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* 4 USART.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff400 {
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
};
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
};
pinctrl_usart3_sck: usart3_sck-0 {
atmel,pins =
<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
};
};
};
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/sama5d3.dtsi
View file @ 21604cdc
This diff is collapsed.
arch/arm/boot/dts/sama5d31.dtsi 0 → 100644
View file @ 21604cdc
/*
* sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_lcd.dtsi"
#include "sama5d3_emac.dtsi"
#include "sama5d3_mci2.dtsi"
#include "sama5d3_uart.dtsi"
/ {
compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5";
};
arch/arm/boot/dts/sama5d31ek.dts
View file @ 21604cdc
......@@ -7,12 +7,13 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d31.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D31-EK";
compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
......
arch/arm/boot/dts/sama5d33.dtsi 0 → 100644
View file @ 21604cdc
/*
* sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_lcd.dtsi"
#include "sama5d3_gmac.dtsi"
/ {
compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5";
};
arch/arm/boot/dts/sama5d33ek.dts
View file @ 21604cdc
......@@ -7,12 +7,13 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d33.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D33-EK";
compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
......
arch/arm/boot/dts/sama5d34.dtsi 0 → 100644
View file @ 21604cdc
/*
* sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_lcd.dtsi"
#include "sama5d3_gmac.dtsi"
#include "sama5d3_can.dtsi"
#include "sama5d3_mci2.dtsi"
/ {
compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5";
};
arch/arm/boot/dts/sama5d34ek.dts
View file @ 21604cdc
......@@ -7,12 +7,13 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d34.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
/ {
model = "Atmel SAMA5D34-EK";
compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
......
arch/arm/boot/dts/sama5d35.dtsi 0 → 100644
View file @ 21604cdc
/*
* sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
#include "sama5d3_gmac.dtsi"
#include "sama5d3_emac.dtsi"
#include "sama5d3_can.dtsi"
#include "sama5d3_mci2.dtsi"
#include "sama5d3_uart.dtsi"
#include "sama5d3_tcb1.dtsi"
/ {
compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5";
};
arch/arm/boot/dts/sama5d35ek.dts
View file @ 21604cdc
......@@ -7,11 +7,12 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d35.dtsi"
#include "sama5d3xmb.dtsi"
/ {
model = "Atmel SAMA5D35-EK";
compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5";
ahb {
apb {
......
arch/arm/boot/dts/sama5d3_can.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* CAN support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
can0 {
pinctrl_can0_rx_tx: can0_rx_tx {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
};
};
can1 {
pinctrl_can1_rx_tx: can1_rx_tx {
atmel,pins =
<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
};
};
};
can0: can@f000c000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf000c000 0x300>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
status = "disabled";
};
can1: can@f8010000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8010000 0x300>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/sama5d3_emac.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* Ethernet.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
macb1 {
pinctrl_macb1_rmii: macb1_rmii-0 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
};
};
};
macb1: ethernet@f802c000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/sama5d3_gmac.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* Gigabit Ethernet.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
macb0 {
pinctrl_macb0_data_rgmii: macb0_data_rgmii {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
};
pinctrl_macb0_data_gmii: macb0_data_gmii {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
};
pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
};
pinctrl_macb0_signal_gmii: macb0_signal_gmii {
atmel,pins =
<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
};
};
};
macb0: ethernet@f0028000 {
compatible = "cdns,pc302-gem", "cdns,gem";
reg = <0xf0028000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/sama5d3_lcd.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* LCD support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
lcd {
pinctrl_lcd: lcd-0 {
atmel,pins =
<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
};
};
};
};
};
};
arch/arm/boot/dts/sama5d3_mci2.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* 3 MMC ports
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
mmc2 {
pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
atmel,pins =
<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
};
pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
atmel,pins =
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
};
};
};
mmc2: mmc@f8004000 {
compatible = "atmel,hsmci";
reg = <0xf8004000 0x600>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
arch/arm/boot/dts/sama5d3_tcb1.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* 2 TC blocks.
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
tcb1 = &tcb1;
};
ahb {
apb {
tcb1: timer@f8014000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8014000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
};
};
};
};
arch/arm/boot/dts/sama5d3_uart.dtsi 0 → 100644
View file @ 21604cdc
/*
* at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
* UART support
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* Licensed under GPLv2.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
ahb {
apb {
pinctrl@fffff200 {
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
};
};
};
uart0: serial@f0024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf0024000 0x200>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
status = "disabled";
};
uart1: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/sama5d3xcm.dtsi
View file @ 21604cdc
......@@ -6,7 +6,6 @@
*
* Licensed under GPLv2 or later.
*/
#include "sama5d3.dtsi"
/ {
compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
......
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
View file @ 21604cdc
......@@ -653,6 +653,7 @@ fsmc: flash@40000000 {
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
clocks = <&hclksmc>;
status = "okay";
timings = /bits/ 8 <0 0 0 0x10 0x0a 0>;
partition@0 {
label = "X-Loader(NAND)";
......@@ -707,8 +708,14 @@ i2c0 {
pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
stw4811@2d {
compatible = "st,stw4811";
reg = <0x2d>;
compatible = "st,stw4811";
reg = <0x2d>;
vmmc_regulator: vmmc {
compatible = "st,stw481x-vmmc";
regulator-name = "VMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
......@@ -839,6 +846,7 @@ mmcsd: sdi@101f6000 {
cd-inverted;
pinctrl-names = "default";
pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
vmmc-supply = <&vmmc_regulator>;
};
};
};
arch/arm/common/Makefile
View file @ 21604cdc
......@@ -6,7 +6,6 @@ obj-y += firmware.o
obj-$(CONFIG_ICST) += icst.o
obj-$(CONFIG_SA1111) += sa1111.o
obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
obj-$(CONFIG_DMABOUNCE) += dmabounce.o
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
......
arch/arm/common/via82c505.c deleted 100644 → 0
View file @ beb5bfe4
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <asm/mach/pci.h>
#define MAX_SLOTS 7
#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
static int
via82c505_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *value)
{
outl(CONFIG_CMD(bus,devfn,where),0xCF8);
switch (size) {
case 1:
*value=inb(0xCFC + (where&3));
break;
case 2:
*value=inw(0xCFC + (where&2));
break;
case 4:
*value=inl(0xCFC);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int
via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 value)
{
outl(CONFIG_CMD(bus,devfn,where),0xCF8);
switch (size) {
case 1:
outb(value, 0xCFC + (where&3));
break;
case 2:
outw(value, 0xCFC + (where&2));
break;
case 4:
outl(value, 0xCFC);
break;
}
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops via82c505_ops = {
.read = via82c505_read_config,
.write = via82c505_write_config,
};
void __init via82c505_preinit(void)
{
printk(KERN_DEBUG "PCI: VIA 82c505\n");
if (!request_region(0xA8,2,"via config")) {
printk(KERN_WARNING"VIA 82c505: Unable to request region 0xA8\n");
return;
}
if (!request_region(0xCF8,8,"pci config")) {
printk(KERN_WARNING"VIA 82c505: Unable to request region 0xCF8\n");
release_region(0xA8, 2);
return;
}
/* Enable compatible Mode */
outb(0x96,0xA8);
outb(0x18,0xA9);
outb(0x93,0xA8);
outb(0xd0,0xA9);
}
int __init via82c505_setup(int nr, struct pci_sys_data *sys)
{
return (nr == 0);
}
arch/arm/configs/shark_defconfig deleted 100644 → 0
View file @ beb5bfe4
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_SHARK=y
CONFIG_LEDS=y
CONFIG_LEDS_TIMER=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECD=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_NET_PCI=y
CONFIG_CS89x0=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_PRINTER=m
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_CYBER2000=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_SOUND=m
CONFIG_SOUND_PRIME=m
CONFIG_SOUND_OSS=m
CONFIG_SOUND_SB=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFSD=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_ISO8859_1=m
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_DEBUG_USER=y
arch/arm/include/asm/mach/pci.h
View file @ 21604cdc
......@@ -106,8 +106,4 @@ extern int dc21285_setup(int nr, struct pci_sys_data *);
extern void dc21285_preinit(void);
extern void dc21285_postinit(void);
extern struct pci_ops via82c505_ops;
extern int via82c505_setup(int nr, struct pci_sys_data *);
extern void via82c505_init(void *sysdata);
#endif /* __ASM_MACH_PCI_H */
arch/arm/include/asm/sched_clock.h deleted 100644 → 0
View file @ beb5bfe4
/* You shouldn't include this file. Use linux/sched_clock.h instead.
* Temporary file until all asm/sched_clock.h users are gone
*/
#include <linux/sched_clock.h>
arch/arm/kernel/time.c
View file @ 21604cdc
......@@ -11,25 +11,26 @@
* This file contains the ARM-specific time handling details:
* reading the RTC at bootup, etc...
*/
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/profile.h>
#include <linux/sched.h>
#include <linux/sched_clock.h>
#include <linux/smp.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/errno.h>
#include <linux/profile.h>
#include <linux/timer.h>
#include <linux/clocksource.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
#include <asm/thread_info.h>
#include <asm/stacktrace.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/stacktrace.h>
#include <asm/thread_info.h>
#if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \
defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE)
......@@ -116,8 +117,12 @@ int __init register_persistent_clock(clock_access_fn read_boot,
void __init time_init(void)
{
if (machine_desc->init_time)
if (machine_desc->init_time) {
machine_desc->init_time();
else
} else {
#ifdef CONFIG_COMMON_CLK
of_clk_init(NULL);
#endif
clocksource_of_init();
}
}
arch/arm/lib/Makefile
View file @ 21604cdc
......@@ -41,7 +41,6 @@ else
endif
lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
lib-$(CONFIG_ARCH_SHARK) += io-shark.o
$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S
......
arch/arm/lib/io-shark.c deleted 100644 → 0
View file @ beb5bfe4
/*
* linux/arch/arm/lib/io-shark.c
*
* by Alexander Schulz
*
* derived from:
* linux/arch/arm/lib/io-ebsa.S
* Copyright (C) 1995, 1996 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
arch/arm/mach-at91/board-cam60.c
View file @ 21604cdc
......@@ -112,7 +112,7 @@ static struct spi_board_info cam60_spi_devices[] __initdata = {
/*
* MACB Ethernet device
*/
static struct __initdata macb_platform_data cam60_macb_data = {
static struct macb_platform_data cam60_macb_data __initdata = {
.phy_irq_pin = AT91_PIN_PB5,
.is_rmii = 0,
};
......
arch/arm/mach-at91/board-dt-rm9200.c
View file @ 21604cdc
......@@ -14,7 +14,6 @@
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/setup.h>
#include <asm/irq.h>
......@@ -36,11 +35,6 @@ static void __init at91rm9200_dt_init_irq(void)
of_irq_init(irq_of_match);
}
static void __init at91rm9200_dt_device_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *at91rm9200_dt_board_compat[] __initdata = {
"atmel,at91rm9200",
NULL
......@@ -52,6 +46,5 @@ DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
.handle_irq = at91_aic_handle_irq,
.init_early = at91rm9200_dt_initialize,
.init_irq = at91rm9200_dt_init_irq,
.init_machine = at91rm9200_dt_device_init,
.dt_compat = at91rm9200_dt_board_compat,
MACHINE_END
arch/arm/mach-at91/board-dt-sam9.c
View file @ 21604cdc
......@@ -13,7 +13,6 @@
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/setup.h>
#include <asm/irq.h>
......@@ -37,11 +36,6 @@ static void __init at91_dt_init_irq(void)
of_irq_init(irq_of_match);
}
static void __init at91_dt_device_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *at91_dt_board_compat[] __initdata = {
"atmel,at91sam9",
NULL
......@@ -54,6 +48,5 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
.handle_irq = at91_aic_handle_irq,
.init_early = at91_dt_initialize,
.init_irq = at91_dt_init_irq,
.init_machine = at91_dt_device_init,
.dt_compat = at91_dt_board_compat,
MACHINE_END
arch/arm/mach-bcm/board_bcm281xx.c
View file @ 21604cdc
......@@ -68,7 +68,6 @@ static void __init board_init(void)
static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, };
DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
.init_time = clocksource_of_init,
.init_machine = board_init,
.restart = bcm_kona_restart,
.dt_compat = bcm11351_dt_compat,
......
arch/arm/mach-bcm2835/bcm2835.c
View file @ 21604cdc
......@@ -18,7 +18,6 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/clk/bcm2835.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -134,7 +133,6 @@ DT_MACHINE_START(BCM2835, "BCM2835")
.init_irq = bcm2835_init_irq,
.handle_irq = bcm2835_handle_irq,
.init_machine = bcm2835_init,
.init_time = clocksource_of_init,
.restart = bcm2835_restart,
.dt_compat = bcm2835_compat
MACHINE_END
arch/arm/mach-clps711x/common.c
View file @ 21604cdc
......@@ -29,12 +29,12 @@
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/clk-provider.h>
#include <linux/sched_clock.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/sched_clock.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
......
arch/arm/mach-dove/board-dt.c
View file @ 21604cdc
......@@ -10,17 +10,13 @@
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/arch.h>
#include <mach/dove.h>
#include <mach/pm.h>
#include <plat/common.h>
#include <plat/irq.h>
#include "common.h"
/*
......@@ -45,12 +41,6 @@ static void __init dove_legacy_clk_init(void)
of_clk_get_from_provider(&clkspec));
}
static void __init dove_dt_time_init(void)
{
of_clk_init(NULL);
clocksource_of_init();
}
static void __init dove_dt_init_early(void)
{
mvebu_mbus_init("marvell,dove-mbus",
......@@ -84,7 +74,6 @@ static const char * const dove_dt_board_compat[] = {
DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
.map_io = dove_map_io,
.init_early = dove_dt_init_early,
.init_time = dove_dt_time_init,
.init_machine = dove_dt_init,
.restart = dove_restart,
.dt_compat = dove_dt_board_compat,
......
arch/arm/mach-exynos/Kconfig
View file @ 21604cdc
......@@ -14,19 +14,28 @@ menu "SAMSUNG EXYNOS SoCs Support"
config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4"
default y
select ARM_AMBA
select CLKSRC_OF
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
select CPU_EXYNOS4210
select GIC_NON_BANKED
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select S5P_DEV_MFC
help
Samsung EXYNOS4 SoCs based systems
config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
select ARM_AMBA
select CLKSRC_OF
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select PINCTRL
select USB_ARCH_HAS_XHCI
help
Samsung EXYNOS5 (Cortex-A15) SoC based systems
......@@ -110,35 +119,6 @@ config SOC_EXYNOS5440
help
Enable EXYNOS5440 SoC support
comment "Flattened Device Tree based board for EXYNOS SoCs"
config MACH_EXYNOS4_DT
bool "Samsung Exynos4 Machine using device tree"
default y
depends on ARCH_EXYNOS4
select ARM_AMBA
select CLKSRC_OF
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
select CPU_EXYNOS4210
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
select S5P_DEV_MFC
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the Exynos4 SoC based board.
Note: This is under development and not all peripherals can be supported
with this machine file.
config MACH_EXYNOS5_DT
bool "SAMSUNG EXYNOS5 Machine using device tree"
default y
depends on ARCH_EXYNOS5
select ARM_AMBA
select CLKSRC_OF
select USB_ARCH_HAS_XHCI
help
Machine support for Samsung EXYNOS5 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS5 SoC based board.
endmenu
endif
arch/arm/mach-exynos/Makefile
View file @ 21604cdc
......@@ -32,5 +32,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
# machine support
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o
obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o
arch/arm/mach-exynos/common.c
View file @ 21604cdc
......@@ -26,8 +26,6 @@
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>
#include <linux/clk-provider.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/chained_irq.h>
......@@ -367,12 +365,6 @@ static void __init exynos5_map_io(void)
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}
void __init exynos_init_time(void)
{
of_clk_init(NULL);
clocksource_of_init();
}
struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
......
arch/arm/mach-exynos/common.h
View file @ 21604cdc
......@@ -16,7 +16,6 @@
#include <linux/of.h>
void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
void exynos_init_time(void);
struct map_desc;
void exynos_init_io(void);
......
arch/arm/mach-exynos/mach-exynos4-dt.c
View file @ 21604cdc
......@@ -11,12 +11,8 @@
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
#include <linux/serial_core.h>
#include <linux/memblock.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <plat/mfc.h>
......@@ -54,7 +50,6 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
.init_early = exynos_firmware_init,
.init_machine = exynos4_dt_machine_init,
.init_late = exynos_init_late,
.init_time = exynos_init_time,
.dt_compat = exynos4_dt_compat,
.restart = exynos4_restart,
.reserve = exynos4_reserve,
......
arch/arm/mach-exynos/mach-exynos5-dt.c
View file @ 21604cdc
......@@ -11,14 +11,10 @@
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
#include <linux/memblock.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <mach/regs-pmu.h>
#include <plat/cpu.h>
#include <plat/mfc.h>
#include "common.h"
......@@ -76,7 +72,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
.map_io = exynos_init_io,
.init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
.init_time = exynos_init_time,
.dt_compat = exynos5_dt_compat,
.restart = exynos5_restart,
.reserve = exynos5_reserve,
......
arch/arm/mach-gemini/time.c
View file @ 21604cdc
......@@ -13,6 +13,8 @@
#include <mach/hardware.h>
#include <mach/global_reg.h>
#include <asm/mach/time.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
/*
* Register definitions for the timers
......@@ -33,19 +35,89 @@
#define TIMER_3_CR_CLOCK (1 << 7)
#define TIMER_3_CR_INT (1 << 8)
static unsigned int tick_rate;
static int gemini_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
u32 cr;
cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
/* This may be overdoing it, feel free to test without this */
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
/* Set next event */
writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
return 0;
}
static void gemini_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
u32 cr;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* Start the timer */
writel(period,
TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
writel(period,
TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
cr |= TIMER_2_CR_ENABLE;
cr |= TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
/*
* Disable also for oneshot: the set_next() call will
* arm the timer instead.
*/
cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
cr &= ~TIMER_2_CR_ENABLE;
cr &= ~TIMER_2_CR_INT;
writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
break;
default:
break;
}
}
/* Use TIMER2 as clock event */
static struct clock_event_device gemini_clockevent = {
.name = "TIMER2",
.rating = 300, /* Reasonably fast and accurate clock event */
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = gemini_timer_set_next_event,
.set_mode = gemini_timer_set_mode,
};
/*
* IRQ handler for the timer
*/
static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
{
timer_tick();
struct clock_event_device *evt = &gemini_clockevent;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction gemini_timer_irq = {
.name = "Gemini Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER,
.flags = IRQF_TIMER,
.handler = gemini_timer_interrupt,
};
......@@ -54,9 +126,9 @@ static struct irqaction gemini_timer_irq = {
*/
void __init gemini_timer_init(void)
{
unsigned int tick_rate, reg_v;
u32 reg_v;
reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS));
reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS));
tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000;
printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000);
......@@ -82,8 +154,17 @@ void __init gemini_timer_init(void)
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMER2, &gemini_timer_irq);
/* Start the timer */
__raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
__raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
__raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
/* Enable and use TIMER1 as clock source */
writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)));
writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE)));
writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)),
"TIMER1", tick_rate, 300, 32,
clocksource_mmio_readl_up))
pr_err("timer: failed to initialize gemini clock source\n");
/* Configure and register the clockevent */
clockevents_config_and_register(&gemini_clockevent, tick_rate,
1, 0xffffffff);
}
arch/arm/mach-highbank/Kconfig
View file @ 21604cdc
......@@ -12,7 +12,6 @@ config ARCH_HIGHBANK
select ARM_GIC
select ARM_TIMER_SP804
select CACHE_L2X0
select CLKDEV_LOOKUP
select COMMON_CLK
select CPU_V7
select GENERIC_CLOCKEVENTS
......
arch/arm/mach-highbank/highbank.c
View file @ 21604cdc
......@@ -24,7 +24,6 @@
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/amba/bus.h>
#include <linux/clk-provider.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
......@@ -83,20 +82,6 @@ static void __init highbank_init_irq(void)
}
}
static void __init highbank_timer_init(void)
{
struct device_node *np;
/* Map system registers */
np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
sregs_base = of_iomap(np, 0);
WARN_ON(!sregs_base);
of_clk_init(NULL);
clocksource_of_init();
}
static void highbank_power_off(void)
{
highbank_set_pwr_shutdown();
......@@ -155,6 +140,13 @@ static struct notifier_block highbank_platform_nb = {
static void __init highbank_init(void)
{
struct device_node *np;
/* Map system registers */
np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
sregs_base = of_iomap(np, 0);
WARN_ON(!sregs_base);
pm_power_off = highbank_power_off;
highbank_pm_init();
......@@ -176,7 +168,6 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
#endif
.smp = smp_ops(highbank_smp_ops),
.init_irq = highbank_init_irq,
.init_time = highbank_timer_init,
.init_machine = highbank_init,
.dt_compat = highbank_match,
.restart = highbank_restart,
......
arch/arm/mach-imx/Kconfig
View file @ 21604cdc
......@@ -4,8 +4,8 @@ config ARCH_MXC
select ARM_CPU_SUSPEND if PM
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR if !ZBOOT_ROM
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_ALLOCATOR
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
......@@ -92,14 +92,12 @@ config MACH_MX27
config SOC_IMX1
bool
select ARCH_MX1
select COMMON_CLK
select CPU_ARM920T
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX21
bool
select COMMON_CLK
select CPU_ARM926T
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
......@@ -108,7 +106,6 @@ config SOC_IMX25
bool
select ARCH_MX25
select ARCH_MXC_IOMUX_V3
select COMMON_CLK
select CPU_ARM926T
select MXC_AVIC
......@@ -116,7 +113,6 @@ config SOC_IMX27
bool
select ARCH_HAS_CPUFREQ
select ARCH_HAS_OPP
select COMMON_CLK
select CPU_ARM926T
select IMX_HAVE_IOMUX_V1
select MACH_MX27
......@@ -124,7 +120,6 @@ config SOC_IMX27
config SOC_IMX31
bool
select COMMON_CLK
select CPU_V6
select IMX_HAVE_PLATFORM_MXC_RNGA
select MXC_AVIC
......@@ -133,7 +128,6 @@ config SOC_IMX31
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select COMMON_CLK
select CPU_V6K
select HAVE_EPIT
select MXC_AVIC
......@@ -144,7 +138,6 @@ config SOC_IMX5
select ARCH_HAS_CPUFREQ
select ARCH_HAS_OPP
select ARCH_MXC_IOMUX_V3
select COMMON_CLK
select CPU_V7
select MXC_TZIC
......@@ -791,7 +784,6 @@ config SOC_IMX6Q
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
select ARM_GIC
select COMMON_CLK
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
......
arch/arm/mach-imx/clk-imx51-imx53.c
View file @ 21604cdc
......@@ -11,6 +11,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/err.h>
......@@ -131,8 +132,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
{
int i;
of_clk_init(NULL);
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
......@@ -465,12 +464,16 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
return 0;
}
int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
unsigned long rate_ckih1, unsigned long rate_ckih2)
static void __init mx51_clocks_init_dt(struct device_node *np)
{
mx51_clocks_init(0, 0, 0, 0);
}
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
static void __init mx53_clocks_init(struct device_node *np)
{
int i;
unsigned long r;
struct device_node *np;
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
......@@ -529,12 +532,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
pr_err("i.MX53 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
mx5_clocks_common_init(0, 0, 0, 0);
clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
......@@ -566,16 +568,5 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
r = clk_round_rate(clk[usboh3_per_gate], 54000000);
clk_set_rate(clk[usboh3_per_gate], r);
return 0;
}
int __init mx51_clocks_init_dt(void)
{
return mx51_clocks_init(0, 0, 0, 0);
}
int __init mx53_clocks_init_dt(void)
{
return mx53_clocks_init(0, 0, 0, 0);
}
CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
arch/arm/mach-imx/common.h
View file @ 21604cdc
......@@ -63,13 +63,9 @@ extern int mx31_clocks_init(unsigned long fref);
extern int mx35_clocks_init(void);
extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
extern int mx25_clocks_init_dt(void);
extern int mx27_clocks_init_dt(void);
extern int mx31_clocks_init_dt(void);
extern int mx51_clocks_init_dt(void);
extern int mx53_clocks_init_dt(void);
extern struct platform_device *mxc_register_gpio(char *name, int id,
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
extern void mxc_set_cpu_type(unsigned int type);
......
arch/arm/mach-imx/imx51-dt.c
View file @ 21604cdc
......@@ -34,17 +34,11 @@ static const char *imx51_dt_board_compat[] __initdata = {
NULL
};
static void __init imx51_timer_init(void)
{
mx51_clocks_init_dt();
}
DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
.map_io = mx51_map_io,
.init_early = imx51_init_early,
.init_irq = mx51_init_irq,
.handle_irq = imx51_handle_irq,
.init_time = imx51_timer_init,
.init_machine = imx51_dt_init,
.init_late = imx51_init_late,
.dt_compat = imx51_dt_board_compat,
......
arch/arm/mach-imx/mach-imx53.c
View file @ 21604cdc
......@@ -36,17 +36,11 @@ static const char *imx53_dt_board_compat[] __initdata = {
NULL
};
static void __init imx53_timer_init(void)
{
mx53_clocks_init_dt();
}
DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.handle_irq = imx53_handle_irq,
.init_time = imx53_timer_init,
.init_machine = imx53_dt_init,
.init_late = imx53_init_late,
.dt_compat = imx53_dt_board_compat,
......
arch/arm/mach-imx/mach-imx6q.c
View file @ 21604cdc
......@@ -11,9 +11,7 @@
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/export.h>
......@@ -192,6 +190,9 @@ static void __init imx6q_1588_init(void)
static void __init imx6q_init_machine(void)
{
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
imx6q_revision());
imx6q_enet_phy_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
......@@ -293,14 +294,6 @@ static void __init imx6q_init_irq(void)
irqchip_init();
}
static void __init imx6q_timer_init(void)
{
of_clk_init(NULL);
clocksource_of_init();
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
imx6q_revision());
}
static const char *imx6q_dt_compat[] __initdata = {
"fsl,imx6dl",
"fsl,imx6q",
......@@ -311,7 +304,6 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
.smp = smp_ops(imx_smp_ops),
.map_io = imx6q_map_io,
.init_irq = imx6q_init_irq,
.init_time = imx6q_timer_init,
.init_machine = imx6q_init_machine,
.init_late = imx6q_init_late,
.dt_compat = imx6q_dt_compat,
......
arch/arm/mach-imx/mach-imx6sl.c
View file @ 21604cdc
......@@ -7,7 +7,6 @@
*
*/
#include <linux/clk-provider.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_platform.h>
......@@ -31,11 +30,6 @@ static void __init imx6sl_init_irq(void)
irqchip_init();
}
static void __init imx6sl_timer_init(void)
{
of_clk_init(NULL);
}
static const char *imx6sl_dt_compat[] __initdata = {
"fsl,imx6sl",
NULL,
......@@ -44,7 +38,6 @@ static const char *imx6sl_dt_compat[] __initdata = {
DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
.map_io = debug_ll_io_init,
.init_irq = imx6sl_init_irq,
.init_time = imx6sl_timer_init,
.init_machine = imx6sl_init_machine,
.dt_compat = imx6sl_dt_compat,
.restart = mxc_restart,
......
arch/arm/mach-imx/mach-vf610.c
View file @ 21604cdc
......@@ -8,9 +8,7 @@
*/
#include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <linux/clk-provider.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
......@@ -28,12 +26,6 @@ static void __init vf610_init_irq(void)
irqchip_init();
}
static void __init vf610_init_time(void)
{
of_clk_init(NULL);
clocksource_of_init();
}
static const char *vf610_dt_compat[] __initdata = {
"fsl,vf610",
NULL,
......@@ -41,7 +33,6 @@ static const char *vf610_dt_compat[] __initdata = {
DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
.init_irq = vf610_init_irq,
.init_time = vf610_init_time,
.init_machine = vf610_init_machine,
.dt_compat = vf610_dt_compat,
.restart = mxc_restart,
......
arch/arm/mach-kirkwood/board-dt.c
View file @ 21604cdc
......@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/dma-mapping.h>
#include <linux/irqchip.h>
#include <linux/kexec.h>
......@@ -66,12 +65,6 @@ static void __init kirkwood_legacy_clk_init(void)
clk_prepare_enable(clk);
}
static void __init kirkwood_dt_time_init(void)
{
of_clk_init(NULL);
clocksource_of_init();
}
static void __init kirkwood_dt_init_early(void)
{
mvebu_mbus_init("marvell,kirkwood-mbus",
......@@ -122,7 +115,6 @@ DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
/* Maintainer: Jason Cooper <jason@lakedaemon.net> */
.map_io = kirkwood_map_io,
.init_early = kirkwood_dt_init_early,
.init_time = kirkwood_dt_time_init,
.init_machine = kirkwood_dt_init,
.restart = kirkwood_restart,
.dt_compat = kirkwood_dt_board_compat,
......
arch/arm/mach-msm/Kconfig
View file @ 21604cdc
if ARCH_MSM
comment "Qualcomm MSM SoC Type"
depends on (ARCH_MSM8X60 || ARCH_MSM8960)
depends on ARCH_MSM_DT
choice
prompt "Qualcomm MSM SoC Type"
default ARCH_MSM7X00A
depends on !(ARCH_MSM8X60 || ARCH_MSM8960)
depends on !ARCH_MSM_DT
config ARCH_MSM7X00A
bool "MSM7x00A / MSM7x01A"
......@@ -49,7 +49,6 @@ config ARCH_MSM8X60
select GPIO_MSM_V2
select HAVE_SMP
select MSM_SCM if SMP
select USE_OF
config ARCH_MSM8960
bool "MSM8960"
......@@ -58,6 +57,11 @@ config ARCH_MSM8960
select HAVE_SMP
select GPIO_MSM_V2
select MSM_SCM if SMP
config ARCH_MSM_DT
def_bool y
depends on (ARCH_MSM8X60 || ARCH_MSM8960)
select SPARSE_IRQ
select USE_OF
config MSM_HAS_DEBUG_UART_HS
......@@ -68,6 +72,7 @@ config MSM_SOC_REV_A
config ARCH_MSM_ARM11
bool
config ARCH_MSM_SCORPION
bool
......@@ -75,6 +80,7 @@ config MSM_VIC
bool
menu "Qualcomm MSM Board Type"
depends on !ARCH_MSM_DT
config MACH_HALIBUT
depends on ARCH_MSM
......@@ -122,6 +128,7 @@ config MSM_SMD
config MSM_GPIOMUX
bool
depends on !ARCH_MSM_DT
help
Support for MSM V1 TLMM GPIOMUX architecture.
......
arch/arm/mach-msm/Makefile
View file @ 21604cdc
......@@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o
obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
arch/arm/mach-msm/board-dt-8660.c deleted 100644 → 0
View file @ beb5bfe4
/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
static void __init msm8x60_init_late(void)
{
smd_debugfs_init();
}
static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
{}
};
static void __init msm8x60_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
msm_auxdata_lookup, NULL);
}
static const char *msm8x60_fluid_match[] __initdata = {
"qcom,msm8660-fluid",
"qcom,msm8660-surf",
NULL
};
DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
.smp = smp_ops(msm_smp_ops),
.init_machine = msm8x60_dt_init,
.init_late = msm8x60_init_late,
.dt_compat = msm8x60_fluid_match,
MACHINE_END
arch/arm/mach-msm/board-dt-8960.c → arch/arm/mach-msm/board-dt.c
View file @ 21604cdc
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
......@@ -11,6 +11,7 @@
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
......@@ -18,18 +19,14 @@
#include "common.h"
static void __init msm_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const msm8960_dt_match[] __initconst = {
static const char * const msm_dt_match[] __initconst = {
"qcom,msm8660-fluid",
"qcom,msm8660-surf",
"qcom,msm8960-cdp",
NULL
};
DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
.smp = smp_ops(msm_smp_ops),
.init_machine = msm_dt_init,
.dt_compat = msm8960_dt_match,
.dt_compat = msm_dt_match,
MACHINE_END
arch/arm/mach-msm/include/mach/irqs-8960.h deleted 100644 → 0
View file @ beb5bfe4
This diff is collapsed.
arch/arm/mach-msm/include/mach/irqs-8x60.h deleted 100644 → 0
View file @ beb5bfe4
This diff is collapsed.
arch/arm/mach-msm/include/mach/irqs.h
View file @ 21604cdc
......@@ -24,11 +24,6 @@
#elif defined(CONFIG_ARCH_QSD8X50)
#include "irqs-8x50.h"
#include "sirc.h"
#elif defined(CONFIG_ARCH_MSM8X60)
#include "irqs-8x60.h"
#elif defined(CONFIG_ARCH_MSM8960)
/* TODO: Make these not generic. */
#include "irqs-8960.h"
#elif defined(CONFIG_ARCH_MSM_ARM11)
#include "irqs-7x00.h"
#else
......
arch/arm/mach-mxs/mach-mxs.c
View file @ 21604cdc
......@@ -13,8 +13,6 @@
#include <linux/clk.h>
#include <linux/clk/mxs.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio.h>
......@@ -490,16 +488,6 @@ static void mxs_restart(enum reboot_mode mode, const char *cmd)
soft_restart(0);
}
static void __init mxs_timer_init(void)
{
if (of_machine_is_compatible("fsl,imx23"))
mx23_clocks_init();
else
mx28_clocks_init();
of_clk_init(NULL);
clocksource_of_init();
}
static const char *mxs_dt_compat[] __initdata = {
"fsl,imx28",
"fsl,imx23",
......@@ -508,7 +496,6 @@ static const char *mxs_dt_compat[] __initdata = {
DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
.handle_irq = icoll_handle_irq,
.init_time = mxs_timer_init,
.init_machine = mxs_machine_init,
.init_late = mxs_pm_init,
.dt_compat = mxs_dt_compat,
......
arch/arm/mach-nomadik/cpu-8815.c
View file @ 21604cdc
......@@ -25,15 +25,11 @@
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/clk-nomadik.h>
#include <linux/clocksource.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/mtd/fsmc.h>
#include <linux/gpio.h>
#include <linux/amba/mmci.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -113,50 +109,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
writel(1, srcbase + 0x18);
}
/* Initial value for SRC control register: all timers use MXTAL/8 source */
#define SRC_CR_INIT_MASK 0x00007fff
#define SRC_CR_INIT_VAL 0x2aaa8000
static void __init cpu8815_timer_init_of(void)
{
struct device_node *mtu;
void __iomem *base;
int irq;
u32 src_cr;
/* We need this to be up now */
nomadik_clk_init();
mtu = of_find_node_by_path("/mtu@101e2000");
if (!mtu)
return;
base = of_iomap(mtu, 0);
if (WARN_ON(!base))
return;
irq = irq_of_parse_and_map(mtu, 0);
pr_info("Remapped MTU @ %p, irq: %d\n", base, irq);
/* Configure timer sources in "system reset controller" ctrl reg */
src_cr = readl(base);
src_cr &= SRC_CR_INIT_MASK;
src_cr |= SRC_CR_INIT_VAL;
writel(src_cr, base);
clocksource_of_init();
}
static struct fsmc_nand_timings cpu8815_nand_timings = {
.thiz = 0,
.thold = 0x10,
.twait = 0x0A,
.tset = 0,
};
static struct fsmc_nand_platform_data cpu8815_nand_data = {
.nand_timings = &cpu8815_nand_timings,
};
/*
* The SMSC911x IRQ is connected to a GPIO pin, but the driver expects
* to simply request an IRQ passed as a resource. So the GPIO pin needs
......@@ -189,15 +141,6 @@ static int __init cpu8815_eth_init(void)
}
device_initcall(cpu8815_eth_init);
/*
* TODO:
* cannot be set from device tree, convert to a proper DT
* binding.
*/
static struct mmci_platform_data mmcsd_plat_data = {
.ocr_mask = MMC_VDD_29_30,
};
/*
* This GPIO pin turns on a line that is used to detect card insertion
* on this board.
......@@ -232,24 +175,13 @@ static int __init cpu8815_mmcsd_init(void)
}
device_initcall(cpu8815_mmcsd_init);
/* These are mostly to get the right device names for the clock lookups */
static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
NULL, &cpu8815_nand_data),
OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE,
NULL, &mmcsd_plat_data),
{ /* sentinel */ },
};
static void __init cpu8815_init_of(void)
{
#ifdef CONFIG_CACHE_L2X0
/* At full speed latency must be >=2, so 0x249 in low bits */
l2x0_of_init(0x00730249, 0xfe000fff);
#endif
of_platform_populate(NULL, of_default_bus_match_table,
cpu8815_auxdata_lookup, NULL);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * cpu8815_board_compat[] = {
......@@ -259,7 +191,6 @@ static const char * cpu8815_board_compat[] = {
DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
.map_io = cpu8815_map_io,
.init_time = cpu8815_timer_init_of,
.init_machine = cpu8815_init_of,
.restart = cpu8815_restart,
.dt_compat = cpu8815_board_compat,
......
arch/arm/mach-nspire/nspire.c
View file @ 21604cdc
......@@ -14,11 +14,9 @@
#include <linux/of_platform.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-vic.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
......@@ -65,12 +63,6 @@ static void __init nspire_init(void)
nspire_auxdata, NULL);
}
static void __init nspire_init_time(void)
{
of_clk_init(NULL);
clocksource_of_init();
}
static void nspire_restart(char mode, const char *cmd)
{
void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
......@@ -83,7 +75,6 @@ static void nspire_restart(char mode, const char *cmd)
DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
.dt_compat = nspire_dt_match,
.map_io = nspire_map_io,
.init_time = nspire_init_time,
.init_machine = nspire_init,
.restart = nspire_restart,
MACHINE_END
arch/arm/mach-omap2/Kconfig
View file @ 21604cdc
......@@ -8,7 +8,6 @@ config ARCH_OMAP2
select CPU_V6
select MULTI_IRQ_HANDLER
select SOC_HAS_OMAP2_SDRC
select COMMON_CLK
config ARCH_OMAP3
bool "TI OMAP3"
......@@ -22,7 +21,6 @@ config ARCH_OMAP3
select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE
select SOC_HAS_OMAP2_SDRC
select COMMON_CLK
select USB_ARCH_HAS_EHCI if USB_SUPPORT
config ARCH_OMAP4
......@@ -45,7 +43,6 @@ config ARCH_OMAP4
select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select COMMON_CLK
select ARM_ERRATA_754322
select ARM_ERRATA_775420
......@@ -59,7 +56,6 @@ config SOC_OMAP5
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_SMP
select COMMON_CLK
select HAVE_ARM_ARCH_TIMER
select ARM_ERRATA_798181 if SMP
......@@ -70,7 +66,6 @@ config SOC_AM33XX
select ARM_CPU_SUSPEND if PM
select CPU_V7
select MULTI_IRQ_HANDLER
select COMMON_CLK
config SOC_AM43XX
bool "TI AM43x"
......@@ -79,7 +74,6 @@ config SOC_AM43XX
select ARCH_OMAP2PLUS
select MULTI_IRQ_HANDLER
select ARM_GIC
select COMMON_CLK
select MACH_OMAP_GENERIC
config ARCH_OMAP2PLUS
......@@ -89,11 +83,10 @@ config ARCH_OMAP2PLUS
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_OMAP
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select HAVE_CLK
select OMAP_DM_TIMER
select PINCTRL
select PROC_DEVICETREE if PROC_FS
......
arch/arm/mach-omap2/clkt2xxx_apll.c
View file @ 21604cdc
......@@ -52,7 +52,7 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
r = omap2xxx_cm_get_pll_status();
return ((r & apll_mask) == apll_mask) ? true : false;
}
......@@ -126,7 +126,7 @@ u32 omap2xxx_get_apll_clkin(void)
{
u32 aplls, srate = 0;
aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
aplls = omap2xxx_cm_get_pll_config();
aplls &= OMAP24XX_APLLS_CLKIN_MASK;
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
......
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
View file @ 21604cdc
......@@ -60,8 +60,7 @@ unsigned long omap2xxx_clk_get_core_rate(void)
core_clk = omap2_get_dpll_rate(dpll_core_ck);
v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
v &= OMAP24XX_CORE_CLK_SRC_MASK;
v = omap2xxx_cm_get_core_clk_src();
if (v == CORE_CLK_SRC_32K)
core_clk = 32768;
......@@ -79,8 +78,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
{
u32 high, low, core_clk_src;
core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
core_clk_src = omap2xxx_cm_get_core_clk_src();
if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
high = curr_prcm_set->dpll_speed * 2;
......@@ -120,8 +118,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
const struct dpll_data *dd;
cur_rate = omap2xxx_clk_get_core_rate();
mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
mult &= OMAP24XX_CORE_CLK_SRC_MASK;
mult = omap2xxx_cm_get_core_clk_src();
if ((rate == (cur_rate / 2)) && (mult == 2)) {
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
......@@ -145,7 +142,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
dd->div1_mask);
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
if (rate > low) {
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
......
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View file @ 21604cdc
......@@ -98,7 +98,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
u32 cur_rate, done_rate, bypass = 0, tmp;
u32 cur_rate, done_rate, bypass = 0;
const struct prcm_config *prcm;
unsigned long found_speed = 0;
unsigned long flags;
......@@ -141,23 +141,11 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
else
done_rate = CORE_CLK_SRC_DPLL;
/* MPU divider */
omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
/* dsp + iva1 div(2420), iva2.1(2430) */
omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
OMAP24XX_DSP_MOD, CM_CLKSEL);
omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
/* Major subsystem dividers */
tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
CM_CLKSEL1);
if (cpu_is_omap2430())
omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
OMAP2430_MDM_MOD, CM_CLKSEL);
omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,
prcm->cm_clksel_dsp,
prcm->cm_clksel_gfx,
prcm->cm_clksel1_core,
prcm->cm_clksel_mdm);
/* x2 to enter omap2xxx_sdrc_init_params() */
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
......
arch/arm/mach-omap2/clock.c
View file @ 21604cdc
......@@ -542,6 +542,44 @@ int omap2_clk_disable_autoidle_all(void)
return 0;
}
/**
* omap2_clk_deny_idle - disable autoidle on an OMAP clock
* @clk: struct clk * to disable autoidle for
*
* Disable autoidle on an OMAP clock.
*/
int omap2_clk_deny_idle(struct clk *clk)
{
struct clk_hw_omap *c;
if (__clk_get_flags(clk) & CLK_IS_BASIC)
return -EINVAL;
c = to_clk_hw_omap(__clk_get_hw(clk));
if (c->ops && c->ops->deny_idle)
c->ops->deny_idle(c);
return 0;
}
/**
* omap2_clk_allow_idle - enable autoidle on an OMAP clock
* @clk: struct clk * to enable autoidle for
*
* Enable autoidle on an OMAP clock.
*/
int omap2_clk_allow_idle(struct clk *clk)
{
struct clk_hw_omap *c;
if (__clk_get_flags(clk) & CLK_IS_BASIC)
return -EINVAL;
c = to_clk_hw_omap(__clk_get_hw(clk));
if (c->ops && c->ops->allow_idle)
c->ops->allow_idle(c);
return 0;
}
/**
* omap2_clk_enable_init_clocks - prepare & enable a list of clocks
* @clk_names: ptr to an array of strings of clock names to enable
......
arch/arm/mach-omap2/clock.h
View file @ 21604cdc
......@@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
void omap2_init_clk_hw_omap_clocks(struct clk *clk);
int omap2_clk_enable_autoidle_all(void);
int omap2_clk_disable_autoidle_all(void);
int omap2_clk_allow_idle(struct clk *clk);
int omap2_clk_deny_idle(struct clk *clk);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
......
arch/arm/mach-omap2/cm2xxx.c
View file @ 21604cdc
......@@ -327,6 +327,73 @@ struct clkdm_ops omap2_clkdm_operations = {
.clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
};
int omap2xxx_cm_fclks_active(void)
{
u32 f1, f2;
f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
return (f1 | f2) ? 1 : 0;
}
int omap2xxx_cm_mpu_retention_allowed(void)
{
u32 l;
/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
return 0;
/* Check for UART3. */
l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
if (l & OMAP24XX_EN_UART3_MASK)
return 0;
return 1;
}
u32 omap2xxx_cm_get_core_clk_src(void)
{
u32 v;
v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
v &= OMAP24XX_CORE_CLK_SRC_MASK;
return v;
}
u32 omap2xxx_cm_get_core_pll_config(void)
{
return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
}
u32 omap2xxx_cm_get_pll_config(void)
{
return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
}
u32 omap2xxx_cm_get_pll_status(void)
{
return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
}
void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
{
u32 tmp;
omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
OMAP24XX_CLKSEL_DSS2_MASK;
omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
if (cpu_is_omap2430())
omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
}
/*
*
*/
......
arch/arm/mach-omap2/cm2xxx.h
View file @ 21604cdc
......@@ -62,6 +62,14 @@ extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
u8 idlest_shift);
extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
s16 *prcm_inst, u8 *idlest_reg_id);
extern int omap2xxx_cm_fclks_active(void);
extern int omap2xxx_cm_mpu_retention_allowed(void);
extern u32 omap2xxx_cm_get_core_clk_src(void);
extern u32 omap2xxx_cm_get_core_pll_config(void);
extern u32 omap2xxx_cm_get_pll_config(void);
extern u32 omap2xxx_cm_get_pll_status(void);
extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
u32 mdm);
extern int __init omap2xxx_cm_init(void);
......
arch/arm/mach-omap2/cm3xxx.c
View file @ 21604cdc
......@@ -636,6 +636,28 @@ void omap3_cm_restore_context(void)
OMAP3_CM_CLKOUT_CTRL_OFFSET);
}
void omap3_cm_save_scratchpad_contents(u32 *ptr)
{
*ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
*ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
/*
* As per erratum i671, ROM code does not respect the PER DPLL
* programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
* Then, in anycase, clear these bits to avoid extra latencies.
*/
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
~OMAP3430_AUTO_PERIPH_DPLL_MASK;
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
}
/*
*
*/
......
arch/arm/mach-omap2/cm3xxx.h
View file @ 21604cdc
......@@ -83,6 +83,7 @@ extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
extern void omap3_cm_save_context(void);
extern void omap3_cm_restore_context(void);
extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
extern int __init omap3xxx_cm_init(void);
......
arch/arm/mach-omap2/control.c
View file @ 21604cdc
......@@ -46,17 +46,7 @@ struct omap3_scratchpad {
struct omap3_scratchpad_prcm_block {
u32 prm_clksrc_ctrl;
u32 prm_clksel;
u32 cm_clksel_core;
u32 cm_clksel_wkup;
u32 cm_clken_pll;
u32 cm_autoidle_pll;
u32 cm_clksel1_pll;
u32 cm_clksel2_pll;
u32 cm_clksel3_pll;
u32 cm_clken_pll_mpu;
u32 cm_autoidle_pll_mpu;
u32 cm_clksel1_pll_mpu;
u32 cm_clksel2_pll_mpu;
u32 cm_contents[11];
u32 prcm_block_size;
};
......@@ -347,34 +337,9 @@ void omap3_save_scratchpad_contents(void)
prcm_block_contents.prm_clksel =
omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
OMAP3_PRM_CLKSEL_OFFSET);
prcm_block_contents.cm_clksel_core =
omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
prcm_block_contents.cm_clksel_wkup =
omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
prcm_block_contents.cm_clken_pll =
omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
/*
* As per erratum i671, ROM code does not respect the PER DPLL
* programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
* Then, in anycase, clear these bits to avoid extra latencies.
*/
prcm_block_contents.cm_autoidle_pll =
omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
~OMAP3430_AUTO_PERIPH_DPLL_MASK;
prcm_block_contents.cm_clksel1_pll =
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll =
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
prcm_block_contents.cm_clksel3_pll =
omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
prcm_block_contents.cm_clken_pll_mpu =
omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
prcm_block_contents.cm_autoidle_pll_mpu =
omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
prcm_block_contents.cm_clksel1_pll_mpu =
omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
prcm_block_contents.cm_clksel2_pll_mpu =
omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
prcm_block_contents.prcm_block_size = 0x0;
/* Populate the SDRC block contents */
......@@ -604,4 +569,15 @@ int omap3_ctrl_save_padconf(void)
return 0;
}
/**
* omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
*
* Sets the bootmode for IVA2 to idle. This is needed by the PM code to
* force disable IVA2 so that it does not prevent any low-power states.
*/
void omap3_ctrl_set_iva_bootmode_idle(void)
{
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
OMAP343X_CONTROL_IVA2_BOOTMOD);
}
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
arch/arm/mach-omap2/control.h
View file @ 21604cdc
......@@ -427,6 +427,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
extern void omap3_ctrl_set_iva_bootmode_idle(void);
extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad);
#else
......
arch/arm/mach-omap2/mcbsp.c
View file @ 21604cdc
......@@ -25,6 +25,7 @@
#include "soc.h"
#include "omap_device.h"
#include "clock.h"
/*
* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
......@@ -33,22 +34,18 @@
#include "cm3xxx.h"
#include "cm-regbits-34xx.h"
static struct clk *mcbsp_iclks[5];
static int omap3_enable_st_clock(unsigned int id, bool enable)
{
unsigned int w;
/*
* Sidetone uses McBSP ICLK - which must not idle when sidetones
* are enabled or sidetones start sounding ugly.
*/
w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
if (enable)
w &= ~(1 << (id - 2));
return omap2_clk_deny_idle(mcbsp_iclks[id]);
else
w |= 1 << (id - 2);
omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
return 0;
return omap2_clk_allow_idle(mcbsp_iclks[id]);
}
static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
......@@ -58,6 +55,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
struct omap_hwmod *oh_device[2];
struct omap_mcbsp_platform_data *pdata = NULL;
struct platform_device *pdev;
char clk_name[11];
sscanf(oh->name, "mcbsp%d", &id);
......@@ -99,6 +97,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
oh_device[1] = omap_hwmod_lookup((
(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
pdata->enable_st_clock = omap3_enable_st_clock;
sprintf(clk_name, "mcbsp%d_ick", id);
mcbsp_iclks[id] = clk_get(NULL, clk_name);
count++;
}
pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
......
arch/arm/mach-omap2/pm24xx.c
View file @ 21604cdc
......@@ -62,16 +62,6 @@ static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
static struct clk *osc_ck, *emul_ck;
static int omap2_fclks_active(void)
{
u32 f1, f2;
f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
return (f1 | f2) ? 1 : 0;
}
static int omap2_enter_full_retention(void)
{
u32 l;
......@@ -142,17 +132,7 @@ static int sti_console_enabled;
static int omap2_allow_mpu_retention(void)
{
u32 l;
/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
return 0;
/* Check for UART3. */
l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
if (l & OMAP24XX_EN_UART3_MASK)
if (!omap2xxx_cm_mpu_retention_allowed())
return 0;
if (sti_console_enabled)
return 0;
......@@ -188,7 +168,7 @@ static void omap2_enter_mpu_retention(void)
static int omap2_can_sleep(void)
{
if (omap2_fclks_active())
if (omap2xxx_cm_fclks_active())
return 0;
if (__clk_is_enabled(osc_ck))
return 0;
......
arch/arm/mach-omap2/pm34xx.c
View file @ 21604cdc
......@@ -430,8 +430,7 @@ static void __init omap3_iva_idle(void)
OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Set IVA2 boot mode to 'idle' */
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
OMAP343X_CONTROL_IVA2_BOOTMOD);
omap3_ctrl_set_iva_bootmode_idle();
/* Un-reset IVA2 */
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
......
arch/arm/mach-prima2/common.c
View file @ 21604cdc
......@@ -6,7 +6,6 @@
* Licensed under GPLv2 or later.
*/
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/sizes.h>
......@@ -21,13 +20,6 @@ void __init sirfsoc_init_late(void)
sirfsoc_pm_init();
}
static __init void sirfsoc_init_time(void)
{
/* initialize clocking early, we want to set the OS timer */
sirfsoc_of_clk_init();
clocksource_of_init();
}
static __init void sirfsoc_map_io(void)
{
sirfsoc_map_lluart();
......@@ -43,7 +35,6 @@ static const char *atlas6_dt_match[] __initdata = {
DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.map_io = sirfsoc_map_io,
.init_time = sirfsoc_init_time,
.init_late = sirfsoc_init_late,
.dt_compat = atlas6_dt_match,
.restart = sirfsoc_restart,
......@@ -59,7 +50,6 @@ static const char *prima2_dt_match[] __initdata = {
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.map_io = sirfsoc_map_io,
.init_time = sirfsoc_init_time,
.dma_zone_size = SZ_256M,
.init_late = sirfsoc_init_late,
.dt_compat = prima2_dt_match,
......@@ -77,7 +67,6 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.smp = smp_ops(sirfsoc_smp_ops),
.map_io = sirfsoc_map_io,
.init_time = sirfsoc_init_time,
.init_late = sirfsoc_init_late,
.dt_compat = marco_dt_match,
.restart = sirfsoc_restart,
......
arch/arm/mach-prima2/common.h
View file @ 21604cdc
......@@ -23,7 +23,6 @@ extern void sirfsoc_secondary_startup(void);
extern void sirfsoc_cpu_die(unsigned int cpu);
extern void __init sirfsoc_of_irq_init(void);
extern void __init sirfsoc_of_clk_init(void);
extern void sirfsoc_restart(enum reboot_mode, const char *);
extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
......
arch/arm/mach-rockchip/rockchip.c
View file @ 21604cdc
......@@ -19,18 +19,10 @@
#include <linux/init.h>
#include <linux/of_platform.h>
#include <linux/irqchip.h>
#include <linux/dw_apb_timer.h>
#include <linux/clk-provider.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
static void __init rockchip_timer_init(void)
{
of_clk_init(NULL);
clocksource_of_init();
}
static void __init rockchip_dt_init(void)
{
l2x0_of_init(0, ~0UL);
......@@ -47,6 +39,5 @@ static const char * const rockchip_board_dt_compat[] = {
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
.init_machine = rockchip_dt_init,
.init_time = rockchip_timer_init,
.dt_compat = rockchip_board_dt_compat,
MACHINE_END
arch/arm/mach-s3c64xx/Kconfig
View file @ 21604cdc
......@@ -3,16 +3,7 @@
#
# Licensed under GPLv2
# temporary until we can eliminate all drivers using it.
config PLAT_S3C64XX
bool
depends on ARCH_S3C64XX
default y
select PM_GENERIC_DOMAINS
select SAMSUNG_WAKEMASK
help
Base platform code for any Samsung S3C64XX device
if ARCH_S3C64XX
# Configuration options for the S3C6410 CPU
......@@ -306,3 +297,5 @@ config MACH_WLF_CRAGG_6410
select SAMSUNG_GPIO_EXTRA128
help
Machine support for the Wolfson Cragganmore S3C6410 variant.
endif
arch/arm/mach-shark/Makefile deleted 100644 → 0
View file @ beb5bfe4
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := core.o dma.o irq.o pci.o leds.o
obj-m :=
obj-n :=
obj- :=
arch/arm/mach-shark/core.c deleted 100644 → 0
View file @ beb5bfe4
/*
* linux/arch/arm/mach-shark/arch.c
*
* Architecture specific stuff.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
#include <linux/cpu.h>
#include <linux/reboot.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/param.h>
#include <asm/system_misc.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#define ROMCARD_SIZE 0x08000000
#define ROMCARD_START 0x10000000
static void shark_restart(enum reboot_mode mode, const char *cmd)
{
short temp;
/* Reset the Machine via pc[3] of the sequoia chipset */
outw(0x09,0x24);
temp=inw(0x26);
temp = temp | (1<<3) | (1<<10);
outw(0x09,0x24);
outw(temp,0x26);
}
static struct plat_serial8250_port serial_platform_data[] = {
{
.iobase = 0x3f8,
.irq = 4,
.uartclk = 1843200,
.regshift = 0,
.iotype = UPIO_PORT,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
{
.iobase = 0x2f8,
.irq = 3,
.uartclk = 1843200,
.regshift = 0,
.iotype = UPIO_PORT,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
{ },
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
};
static struct resource rtc_resources[] = {
[0] = {
.start = 0x70,
.end = 0x73,
.flags = IORESOURCE_IO,
},
[1] = {
.start = IRQ_ISA_RTC_ALARM,
.end = IRQ_ISA_RTC_ALARM,
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device rtc_device = {
.name = "rtc_cmos",
.id = -1,
.resource = rtc_resources,
.num_resources = ARRAY_SIZE(rtc_resources),
};
static int __init shark_init(void)
{
int ret;
if (machine_is_shark())
{
ret = platform_device_register(&rtc_device);
if (ret) printk(KERN_ERR "Unable to register RTC device: %d\n", ret);
ret = platform_device_register(&serial_device);
if (ret) printk(KERN_ERR "Unable to register Serial device: %d\n", ret);
}
return 0;
}
arch_initcall(shark_init);
extern void shark_init_irq(void);
#define IRQ_TIMER 0
#define HZ_TIME ((1193180 + HZ/2) / HZ)
static irqreturn_t
shark_timer_interrupt(int irq, void *dev_id)
{
timer_tick();
return IRQ_HANDLED;
}
static struct irqaction shark_timer_irq = {
.name = "Shark Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = shark_timer_interrupt,
};
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static void __init shark_timer_init(void)
{
outb(0x34, 0x43); /* binary, mode 0, LSB/MSB, Ch 0 */
outb(HZ_TIME & 0xff, 0x40); /* LSB of count */
outb(HZ_TIME >> 8, 0x40);
setup_irq(IRQ_TIMER, &shark_timer_irq);
}
static void shark_init_early(void)
{
cpu_idle_poll_ctrl(true);
}
MACHINE_START(SHARK, "Shark")
/* Maintainer: Alexander Schulz */
.atag_offset = 0x3000,
.init_early = shark_init_early,
.init_irq = shark_init_irq,
.init_time = shark_timer_init,
.dma_zone_size = SZ_4M,
.restart = shark_restart,
MACHINE_END
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