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Commit 216883a4 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-dt-for-v4.3' of... 

Merge tag 'renesas-dt-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Updates for v4.3" from Simon Horman:

* Configure IRLM mode via DT on r8a7779 SoC
* Use "arm,gic-400" for GIC on r8a777[01349] and r8a73a4 SoCs
* Add pinctrl and gpio-hog for lcdc0 to armadillo800eva board
* EtherAVB DT support for r8a7790 SoC
* Minimal device tree for r8a7793 SoC and its Gose board

* tag 'renesas-dt-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7779: Configure IRLM mode via DT
  ARM: shmobile: r8a7794 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a7793 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a7791 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a7790 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: r8a73a4 dtsi: Use "arm,gic-400" for GIC
  ARM: shmobile: armadillo800eva dts: Add pinctrl and gpio-hog for lcdc0
  ARM: shmobile: r8a7790: add EtherAVB DT support
  ARM: shmobile: r8a7790: add EtherAVB clocks
  ARM: shmobile: r8a7793: add minimal Gose board device tree
  ARM: shmobile: add r8a7793 minimal SoC device tree
parents 3fbf02a8 7bf46d0b
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Showing with 632 additions and 10 deletions
arch/arm/boot/dts/Makefile
View file @ 216883a4
......@@ -516,6 +516,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
......
arch/arm/boot/dts/r8a73a4.dtsi
View file @ 216883a4
......@@ -434,7 +434,7 @@ mmcif1: mmc@ee220000 {
};
gic: interrupt-controller@f1001000 {
compatible = "arm,cortex-a15-gic";
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
......
arch/arm/boot/dts/r8a7740-armadillo800eva.dts
View file @ 216883a4
......@@ -224,6 +224,9 @@ rtc@30 {
};
&pfc {
pinctrl-0 = <&lcd0_pins>;
pinctrl-names = "default";
ether_pins: ether {
renesas,groups = "gether_mii", "gether_int";
renesas,function = "gether";
......@@ -259,6 +262,16 @@ fsia_pins: sounda {
"fsia_data_in_1", "fsia_data_out_0";
renesas,function = "fsia";
};
lcd0_pins: lcd0 {
renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
renesas,function = "lcd0";
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;
gpios = <176 0>;
output-high;
};
};
&tpu {
......
arch/arm/boot/dts/r8a7779.dtsi
View file @ 216883a4
......@@ -148,7 +148,7 @@ gpio6: gpio@ffc46000 {
interrupt-controller;
};
irqpin0: interrupt-controller@fe780010 {
irqpin0: interrupt-controller@fe78001c {
compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
#interrupt-cells = <2>;
status = "disabled";
......@@ -157,7 +157,8 @@ irqpin0: interrupt-controller@fe780010 {
<0xfe780010 4>,
<0xfe780024 4>,
<0xfe780044 4>,
<0xfe780064 4>;
<0xfe780064 4>,
<0xfe780000 4>;
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
0 28 IRQ_TYPE_LEVEL_HIGH
0 29 IRQ_TYPE_LEVEL_HIGH
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ 216883a4
......@@ -113,7 +113,7 @@ cpu7: cpu@7 {
};
gic: interrupt-controller@f1001000 {
compatible = "arm,cortex-a15-gic";
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
......@@ -671,6 +671,16 @@ ether: ethernet@ee700000 {
status = "disabled";
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7790";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7790";
reg = <0 0xee300000 0 0x2000>;
......@@ -1249,16 +1259,18 @@ mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
<&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
>;
clock-output-names =
"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
"sata1", "sata0";
"mlb", "vin3", "vin2", "vin1", "vin0",
"etheravb", "ether", "sata1", "sata0";
};
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ 216883a4
......@@ -70,7 +70,7 @@ cpu1: cpu@1 {
};
gic: interrupt-controller@f1001000 {
compatible = "arm,cortex-a15-gic";
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
......
arch/arm/boot/dts/r8a7793-gose.dts 0 → 100644
View file @ 216883a4
/*
* Device Tree Source for the Gose board
*
* Copyright (C) 2014-2015 Renesas Electronics Corporation
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7793.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Gose";
compatible = "renesas,gose", "renesas,r8a7793";
aliases {
serial0 = &scif0;
serial1 = &scif1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = &scif0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&ether {
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
};
};
&cmt0 {
status = "okay";
};
&scif0 {
status = "okay";
};
&scif1 {
status = "okay";
};
arch/arm/boot/dts/r8a7793.dtsi 0 → 100644
View file @ 216883a4
This diff is collapsed.
arch/arm/boot/dts/r8a7794.dtsi
View file @ 216883a4
......@@ -39,7 +39,7 @@ cpu1: cpu@1 {
};
gic: interrupt-controller@f1001000 {
compatible = "arm,cortex-a7-gic";
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
......
include/dt-bindings/clock/r8a7790-clock.h
View file @ 216883a4
......@@ -108,6 +108,7 @@
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10
#define R8A7790_CLK_VIN0 11
#define R8A7790_CLK_ETHERAVB 12
#define R8A7790_CLK_ETHER 13
#define R8A7790_CLK_SATA1 14
#define R8A7790_CLK_SATA0 15
......
include/dt-bindings/clock/r8a7793-clock.h 0 → 100644
View file @ 216883a4
/*
* r8a7793 clock definition
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
#define __DT_BINDINGS_CLOCK_R8A7793_H__
/* CPG */
#define R8A7793_CLK_MAIN 0
#define R8A7793_CLK_PLL0 1
#define R8A7793_CLK_PLL1 2
#define R8A7793_CLK_PLL3 3
#define R8A7793_CLK_LB 4
#define R8A7793_CLK_QSPI 5
#define R8A7793_CLK_SDH 6
#define R8A7793_CLK_SD0 7
#define R8A7793_CLK_Z 8
#define R8A7793_CLK_RCAN 9
#define R8A7793_CLK_ADSP 10
/* MSTP0 */
#define R8A7793_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7793_CLK_VCP0 1
#define R8A7793_CLK_VPC0 3
#define R8A7793_CLK_SSP1 9
#define R8A7793_CLK_TMU1 11
#define R8A7793_CLK_3DG 12
#define R8A7793_CLK_2DDMAC 15
#define R8A7793_CLK_FDP1_1 18
#define R8A7793_CLK_FDP1_0 19
#define R8A7793_CLK_TMU3 21
#define R8A7793_CLK_TMU2 22
#define R8A7793_CLK_CMT0 24
#define R8A7793_CLK_TMU0 25
#define R8A7793_CLK_VSP1_DU1 27
#define R8A7793_CLK_VSP1_DU0 28
#define R8A7793_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7793_CLK_SCIFA2 2
#define R8A7793_CLK_SCIFA1 3
#define R8A7793_CLK_SCIFA0 4
#define R8A7793_CLK_MSIOF2 5
#define R8A7793_CLK_SCIFB0 6
#define R8A7793_CLK_SCIFB1 7
#define R8A7793_CLK_MSIOF1 8
#define R8A7793_CLK_SCIFB2 16
#define R8A7793_CLK_SYS_DMAC1 18
#define R8A7793_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7793_CLK_TPU0 4
#define R8A7793_CLK_SDHI2 11
#define R8A7793_CLK_SDHI1 12
#define R8A7793_CLK_SDHI0 14
#define R8A7793_CLK_MMCIF0 15
#define R8A7793_CLK_IIC0 18
#define R8A7793_CLK_PCIEC 19
#define R8A7793_CLK_IIC1 23
#define R8A7793_CLK_SSUSB 28
#define R8A7793_CLK_CMT1 29
#define R8A7793_CLK_USBDMAC0 30
#define R8A7793_CLK_USBDMAC1 31
/* MSTP4 */
#define R8A7793_CLK_IRQC 7
/* MSTP5 */
#define R8A7793_CLK_AUDIO_DMAC1 1
#define R8A7793_CLK_AUDIO_DMAC0 2
#define R8A7793_CLK_ADSP_MOD 6
#define R8A7793_CLK_THERMAL 22
#define R8A7793_CLK_PWM 23
/* MSTP7 */
#define R8A7793_CLK_EHCI 3
#define R8A7793_CLK_HSUSB 4
#define R8A7793_CLK_HSCIF2 13
#define R8A7793_CLK_SCIF5 14
#define R8A7793_CLK_SCIF4 15
#define R8A7793_CLK_HSCIF1 16
#define R8A7793_CLK_HSCIF0 17
#define R8A7793_CLK_SCIF3 18
#define R8A7793_CLK_SCIF2 19
#define R8A7793_CLK_SCIF1 20
#define R8A7793_CLK_SCIF0 21
#define R8A7793_CLK_DU1 23
#define R8A7793_CLK_DU0 24
#define R8A7793_CLK_LVDS0 26
/* MSTP8 */
#define R8A7793_CLK_IPMMU_SGX 0
#define R8A7793_CLK_VIN2 9
#define R8A7793_CLK_VIN1 10
#define R8A7793_CLK_VIN0 11
#define R8A7793_CLK_ETHER 13
#define R8A7793_CLK_SATA1 14
#define R8A7793_CLK_SATA0 15
/* MSTP9 */
#define R8A7793_CLK_GPIO7 4
#define R8A7793_CLK_GPIO6 5
#define R8A7793_CLK_GPIO5 7
#define R8A7793_CLK_GPIO4 8
#define R8A7793_CLK_GPIO3 9
#define R8A7793_CLK_GPIO2 10
#define R8A7793_CLK_GPIO1 11
#define R8A7793_CLK_GPIO0 12
#define R8A7793_CLK_RCAN1 15
#define R8A7793_CLK_RCAN0 16
#define R8A7793_CLK_QSPI_MOD 17
#define R8A7793_CLK_I2C5 25
#define R8A7793_CLK_IICDVFS 26
#define R8A7793_CLK_I2C4 27
#define R8A7793_CLK_I2C3 28
#define R8A7793_CLK_I2C2 29
#define R8A7793_CLK_I2C1 30
#define R8A7793_CLK_I2C0 31
/* MSTP10 */
#define R8A7793_CLK_SSI_ALL 5
#define R8A7793_CLK_SSI9 6
#define R8A7793_CLK_SSI8 7
#define R8A7793_CLK_SSI7 8
#define R8A7793_CLK_SSI6 9
#define R8A7793_CLK_SSI5 10
#define R8A7793_CLK_SSI4 11
#define R8A7793_CLK_SSI3 12
#define R8A7793_CLK_SSI2 13
#define R8A7793_CLK_SSI1 14
#define R8A7793_CLK_SSI0 15
#define R8A7793_CLK_SCU_ALL 17
#define R8A7793_CLK_SCU_DVC1 18
#define R8A7793_CLK_SCU_DVC0 19
#define R8A7793_CLK_SCU_SRC9 22
#define R8A7793_CLK_SCU_SRC8 23
#define R8A7793_CLK_SCU_SRC7 24
#define R8A7793_CLK_SCU_SRC6 25
#define R8A7793_CLK_SCU_SRC5 26
#define R8A7793_CLK_SCU_SRC4 27
#define R8A7793_CLK_SCU_SRC3 28
#define R8A7793_CLK_SCU_SRC2 29
#define R8A7793_CLK_SCU_SRC1 30
#define R8A7793_CLK_SCU_SRC0 31
/* MSTP11 */
#define R8A7793_CLK_SCIFA3 6
#define R8A7793_CLK_SCIFA4 7
#define R8A7793_CLK_SCIFA5 8
#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
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