irqchip/qcom-mpm: Support passing a slice of SRAM as reg space
The MPM hardware is accessible from the ARM CPUs through a shared memory region (RPM MSG RAM) which is also concurrently accessed by other kinds of cores on the system like modem, ADSP etc. Modeling this relation in a (somewhat) sane manner in the device tree requires to - either present the MPM as a child of said memory region, which makes little sense, as a mapped memory carveout is not a bus. - define nodes which bleed their register spaces into one another - or passing their slice of the MSG RAM through a property Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as register space for the MPM interrupt controller. The current way of using 'reg' is preserved for backwards compatibility reasons. [ tglx: Massaged changelog ] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20230328-topic-msgram_mpm-v7-2-6ee2bfeaac2c@linaro.org
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