Commit 25a853d0 authored by Ken Xue's avatar Ken Xue Committed by Linus Walleij

Fix inconsistent spinlock of AMD GPIO driver which can be

recognized by static analysis tool smatch. Declare constant
Variables with Sparse's suggestion.
Signed-off-by: default avatarKen Xue <Ken.Xue@amd.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent d480239b
...@@ -29,7 +29,6 @@ ...@@ -29,7 +29,6 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/list.h> #include <linux/list.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf-generic.h>
...@@ -119,8 +118,9 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) ...@@ -119,8 +118,9 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
unsigned debounce) unsigned debounce)
{ {
u32 pin_reg;
u32 time; u32 time;
u32 pin_reg;
int ret = 0;
unsigned long flags; unsigned long flags;
struct amd_gpio *gpio_dev = to_amd_gpio(gc); struct amd_gpio *gpio_dev = to_amd_gpio(gc);
...@@ -166,7 +166,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, ...@@ -166,7 +166,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
pin_reg |= BIT(DB_TMR_LARGE_OFF); pin_reg |= BIT(DB_TMR_LARGE_OFF);
} else { } else {
pin_reg &= ~DB_CNTRl_MASK; pin_reg &= ~DB_CNTRl_MASK;
return -EINVAL; ret = -EINVAL;
} }
} else { } else {
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
...@@ -177,7 +177,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, ...@@ -177,7 +177,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
writel(pin_reg, gpio_dev->base + offset * 4); writel(pin_reg, gpio_dev->base + offset * 4);
spin_unlock_irqrestore(&gpio_dev->lock, flags); spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0; return ret;
} }
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
...@@ -463,14 +463,12 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) ...@@ -463,14 +463,12 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
default: default:
dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
ret = -EINVAL; ret = -EINVAL;
goto exit;
} }
pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
writel(pin_reg, gpio_dev->base + (d->hwirq)*4); writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
spin_unlock_irqrestore(&gpio_dev->lock, flags); spin_unlock_irqrestore(&gpio_dev->lock, flags);
exit:
return ret; return ret;
} }
...@@ -635,8 +633,9 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ...@@ -635,8 +633,9 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned num_configs) unsigned long *configs, unsigned num_configs)
{ {
int i; int i;
u32 pin_reg;
u32 arg; u32 arg;
int ret = 0;
u32 pin_reg;
unsigned long flags; unsigned long flags;
enum pin_config_param param; enum pin_config_param param;
struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
...@@ -675,14 +674,14 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ...@@ -675,14 +674,14 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
default: default:
dev_err(&gpio_dev->pdev->dev, dev_err(&gpio_dev->pdev->dev,
"Invalid config param %04x\n", param); "Invalid config param %04x\n", param);
return -ENOTSUPP; ret = -ENOTSUPP;
} }
writel(pin_reg, gpio_dev->base + pin*4); writel(pin_reg, gpio_dev->base + pin*4);
} }
spin_unlock_irqrestore(&gpio_dev->lock, flags); spin_unlock_irqrestore(&gpio_dev->lock, flags);
return 0; return ret;
} }
static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
...@@ -739,7 +738,7 @@ static struct pinctrl_desc amd_pinctrl_desc = { ...@@ -739,7 +738,7 @@ static struct pinctrl_desc amd_pinctrl_desc = {
static int amd_gpio_probe(struct platform_device *pdev) static int amd_gpio_probe(struct platform_device *pdev)
{ {
int ret = 0; int ret = 0;
u32 irq_base; int irq_base;
struct resource *res; struct resource *res;
struct amd_gpio *gpio_dev; struct amd_gpio *gpio_dev;
......
...@@ -217,13 +217,13 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { ...@@ -217,13 +217,13 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(177, "GPIO_177"), PINCTRL_PIN(177, "GPIO_177"),
}; };
const unsigned i2c0_pins[] = {145, 146}; static const unsigned i2c0_pins[] = {145, 146};
const unsigned i2c1_pins[] = {147, 148}; static const unsigned i2c1_pins[] = {147, 148};
const unsigned i2c2_pins[] = {113, 114}; static const unsigned i2c2_pins[] = {113, 114};
const unsigned i2c3_pins[] = {19, 20}; static const unsigned i2c3_pins[] = {19, 20};
const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; static const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
static const struct amd_pingroup kerncz_groups[] = { static const struct amd_pingroup kerncz_groups[] = {
{ {
......
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