Commit 26b3da0b authored by Kanoj Sarcar's avatar Kanoj Sarcar Committed by David S. Miller

Move VPTE_BASE_foo definitions to common

header instead of scattered all over assembly files.
parent 5804f347
...@@ -565,13 +565,6 @@ setup_tba: /* i0 = is_starfire */ ...@@ -565,13 +565,6 @@ setup_tba: /* i0 = is_starfire */
#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000) #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W) #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
#define VPTE_BASE_SPITFIRE 0xfffffffe00000000
#if 1
#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE
#else
#define VPTE_BASE_CHEETAH 0xffe0000000000000
#endif
mov TSB_REG, %g1 mov TSB_REG, %g1
stxa %g0, [%g1] ASI_DMMU stxa %g0, [%g1] ASI_DMMU
membar #Sync membar #Sync
...@@ -602,8 +595,6 @@ setup_tba: /* i0 = is_starfire */ ...@@ -602,8 +595,6 @@ setup_tba: /* i0 = is_starfire */
clr %g7 clr %g7
#undef KERN_HIGHBITS #undef KERN_HIGHBITS
#undef KERN_LOWBITS #undef KERN_LOWBITS
#undef VPTE_BASE_SPITFIRE
#undef VPTE_BASE_CHEETAH
/* Setup Interrupt globals */ /* Setup Interrupt globals */
wrpr %o1, (PSTATE_IG|PSTATE_IE), %pstate wrpr %o1, (PSTATE_IG|PSTATE_IE), %pstate
......
...@@ -215,13 +215,6 @@ startup_continue: ...@@ -215,13 +215,6 @@ startup_continue:
#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000) #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W) #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
#define VPTE_BASE_SPITFIRE 0xfffffffe00000000
#if 1
#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE
#else
#define VPTE_BASE_CHEETAH 0xffe0000000000000
#endif
mov TSB_REG, %g1 mov TSB_REG, %g1
stxa %g0, [%g1] ASI_DMMU stxa %g0, [%g1] ASI_DMMU
membar #Sync membar #Sync
...@@ -252,8 +245,6 @@ startup_continue: ...@@ -252,8 +245,6 @@ startup_continue:
clr %g7 clr %g7
#undef KERN_HIGHBITS #undef KERN_HIGHBITS
#undef KERN_LOWBITS #undef KERN_LOWBITS
#undef VPTE_BASE_SPITFIRE
#undef VPTE_BASE_CHEETAH
wrpr %o1, 0x0, %pstate wrpr %o1, 0x0, %pstate
ldx [%g6 + TI_TASK], %g4 ldx [%g6 + TI_TASK], %g4
......
...@@ -10,13 +10,6 @@ ...@@ -10,13 +10,6 @@
#include <asm/spitfire.h> #include <asm/spitfire.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#define VPTE_BASE_SPITFIRE 0xfffffffe00000000
#if 1
#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE
#else
#define VPTE_BASE_CHEETAH 0xffe0000000000000
#endif
static __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, static __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start,
unsigned long end) unsigned long end)
{ {
...@@ -42,8 +35,6 @@ static __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long st ...@@ -42,8 +35,6 @@ static __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long st
vpte_base + (e >> (PAGE_SHIFT - 3))); vpte_base + (e >> (PAGE_SHIFT - 3)));
} }
} }
#undef VPTE_BASE_SPITFIRE
#undef VPTE_BASE_CHEETAH
/* Page table allocation/freeing. */ /* Page table allocation/freeing. */
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
......
...@@ -39,9 +39,25 @@ ...@@ -39,9 +39,25 @@
* address that the kernel will allocate out. * address that the kernel will allocate out.
*/ */
#define VA_BITS 44 #define VA_BITS 44
#ifndef __ASSEMBLY__
#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3)) #define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
#else
#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
#endif
#define TASK_SIZE ((unsigned long)-VPTE_SIZE) #define TASK_SIZE ((unsigned long)-VPTE_SIZE)
/*
* The vpte base must be able to hold the entire vpte, half
* of which lives above, and half below, the base. And it
* is placed as close to the highest address range as possible.
*/
#define VPTE_BASE_SPITFIRE (-(VPTE_SIZE/2))
#if 1
#define VPTE_BASE_CHEETAH VPTE_BASE_SPITFIRE
#else
#define VPTE_BASE_CHEETAH 0xffe0000000000000
#endif
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
typedef struct { typedef struct {
......
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