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Commit 27e1c8ee authored by Bjorn Helgaas's avatar Bjorn Helgaas
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Merge branch 'pci/bjorn-pcie-cap' into next 

* pci/bjorn-pcie-cap:
  ath9k: Use standard #defines for PCIe Capability ASPM fields
  iwlwifi: Use standard #defines for PCIe Capability ASPM fields
  iwlwifi: collapse wrapper for pcie_capability_read_word()
  iwlegacy: Use standard #defines for PCIe Capability ASPM fields
  iwlegacy: collapse wrapper for pcie_capability_read_word()
  cxgb3: Use standard #defines for PCIe Capability ASPM fields
  PCI: Add standard PCIe Capability Link ASPM field names
  PCI/portdrv: Use PCI Express Capability accessors
  PCI: Use standard PCIe Capability Link register field names
  PCI: Add and use standard PCI-X Capability register names
parents 72e1e868 a875621e
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Showing with 49 additions and 57 deletions
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
View file @ 27e1c8ee
...@@ -3307,7 +3307,7 @@ static void config_pcie(struct adapter *adap) ...@@ -3307,7 +3307,7 @@ static void config_pcie(struct adapter *adap)
G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE)); G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
log2_width = fls(adap->params.pci.width) - 1; log2_width = fls(adap->params.pci.width) - 1;
acklat = ack_lat[log2_width][pldsize]; acklat = ack_lat[log2_width][pldsize];
if (val & 1) /* check LOsEnable */ if (val & PCI_EXP_LNKCTL_ASPM_L0S) /* check LOsEnable */
acklat += fst_trn_tx * 4; acklat += fst_trn_tx * 4;
rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4; rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;
......
drivers/net/wireless/ath/ath9k/pci.c
View file @ 27e1c8ee
...@@ -125,23 +125,23 @@ static void ath_pci_aspm_init(struct ath_common *common) ...@@ -125,23 +125,23 @@ static void ath_pci_aspm_init(struct ath_common *common)
if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
(AR_SREV_9285(ah))) { (AR_SREV_9285(ah))) {
/* Bluetooth coexistance requires disabling ASPM. */ /* Bluetooth coexistence requires disabling ASPM. */
pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
/* /*
* Both upstream and downstream PCIe components should * Both upstream and downstream PCIe components should
* have the same ASPM settings. * have the same ASPM settings.
*/ */
pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
return; return;
} }
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
ah->aspm_enabled = true; ah->aspm_enabled = true;
/* Initialize PCIe PM and SERDES registers. */ /* Initialize PCIe PM and SERDES registers. */
ath9k_hw_configpcipowersave(ah, false); ath9k_hw_configpcipowersave(ah, false);
......
drivers/net/wireless/iwlegacy/4965.h
View file @ 27e1c8ee
...@@ -917,10 +917,6 @@ struct il4965_scd_bc_tbl { ...@@ -917,10 +917,6 @@ struct il4965_scd_bc_tbl {
/* PCI registers */ /* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT 0x041 #define PCI_CFG_RETRY_TIMEOUT 0x041
/* PCI register values */
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
#define IL4965_DEFAULT_TX_RETRY 15 #define IL4965_DEFAULT_TX_RETRY 15
/* EEPROM */ /* EEPROM */
......
drivers/net/wireless/iwlegacy/common.c
View file @ 27e1c8ee
...@@ -1183,9 +1183,10 @@ EXPORT_SYMBOL(il_power_update_mode); ...@@ -1183,9 +1183,10 @@ EXPORT_SYMBOL(il_power_update_mode);
void void
il_power_initialize(struct il_priv *il) il_power_initialize(struct il_priv *il)
{ {
u16 lctl = il_pcie_link_ctl(il); u16 lctl;
il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
il->power_data.debug_sleep_level_override = -1; il->power_data.debug_sleep_level_override = -1;
...@@ -4233,9 +4234,8 @@ il_apm_init(struct il_priv *il) ...@@ -4233,9 +4234,8 @@ il_apm_init(struct il_priv *il)
* power savings, even without L1. * power savings, even without L1.
*/ */
if (il->cfg->set_l0s) { if (il->cfg->set_l0s) {
lctl = il_pcie_link_ctl(il); pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
PCI_CFG_LINK_CTRL_VAL_L1_EN) {
/* L1-ASPM enabled; disable(!) L0S */ /* L1-ASPM enabled; disable(!) L0S */
il_set_bit(il, CSR_GIO_REG, il_set_bit(il, CSR_GIO_REG,
CSR_GIO_REG_VAL_L0S_ENABLED); CSR_GIO_REG_VAL_L0S_ENABLED);
......
drivers/net/wireless/iwlegacy/common.h
View file @ 27e1c8ee
...@@ -1829,14 +1829,6 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd); ...@@ -1829,14 +1829,6 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
* PCI * * PCI *
*****************************************************/ *****************************************************/
static inline u16
il_pcie_link_ctl(struct il_priv *il)
{
u16 pci_lnk_ctl;
pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &pci_lnk_ctl);
return pci_lnk_ctl;
}
void il_bg_watchdog(unsigned long data); void il_bg_watchdog(unsigned long data);
u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval); u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
...@@ -2434,10 +2426,6 @@ struct il_tfd { ...@@ -2434,10 +2426,6 @@ struct il_tfd {
/* PCI registers */ /* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT 0x041 #define PCI_CFG_RETRY_TIMEOUT 0x041
/* PCI register values */
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
struct il_rate_info { struct il_rate_info {
u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */ u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
......
drivers/net/wireless/iwlwifi/pcie/trans.c
View file @ 27e1c8ee
...@@ -670,21 +670,12 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans) ...@@ -670,21 +670,12 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
/* PCI registers */ /* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT 0x041 #define PCI_CFG_RETRY_TIMEOUT 0x041
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans) static void iwl_apm_config(struct iwl_trans *trans)
{ {
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
u16 pci_lnk_ctl; u16 lctl;
pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
&pci_lnk_ctl);
return pci_lnk_ctl;
}
static void iwl_apm_config(struct iwl_trans *trans)
{
/* /*
* HW bug W/A for instability in PCIe bus L0S->L1 transition. * HW bug W/A for instability in PCIe bus L0S->L1 transition.
* Check if BIOS (or OS) enabled L1-ASPM on this device. * Check if BIOS (or OS) enabled L1-ASPM on this device.
...@@ -693,10 +684,9 @@ static void iwl_apm_config(struct iwl_trans *trans) ...@@ -693,10 +684,9 @@ static void iwl_apm_config(struct iwl_trans *trans)
* If not (unlikely), enable L0S, so there is at least some * If not (unlikely), enable L0S, so there is at least some
* power savings, even without L1. * power savings, even without L1.
*/ */
u16 lctl = iwl_pciexp_link_ctrl(trans);
if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
PCI_CFG_LINK_CTRL_VAL_L1_EN) { if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
/* L1-ASPM enabled; disable(!) L0S */ /* L1-ASPM enabled; disable(!) L0S */
iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
dev_printk(KERN_INFO, trans->dev, dev_printk(KERN_INFO, trans->dev,
...@@ -707,7 +697,7 @@ static void iwl_apm_config(struct iwl_trans *trans) ...@@ -707,7 +697,7 @@ static void iwl_apm_config(struct iwl_trans *trans)
dev_printk(KERN_INFO, trans->dev, dev_printk(KERN_INFO, trans->dev,
"L1 Disabled; Enabling L0S\n"); "L1 Disabled; Enabling L0S\n");
} }
trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
} }
/* /*
......
drivers/pci/pcie/aspm.c
View file @ 27e1c8ee
...@@ -426,7 +426,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) ...@@ -426,7 +426,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
{ {
pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val); pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_ASPMC, val);
} }
static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
...@@ -441,12 +442,12 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) ...@@ -441,12 +442,12 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
return; return;
/* Convert ASPM state to upstream/downstream ASPM register state */ /* Convert ASPM state to upstream/downstream ASPM register state */
if (state & ASPM_STATE_L0S_UP) if (state & ASPM_STATE_L0S_UP)
dwstream |= PCIE_LINK_STATE_L0S; dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
if (state & ASPM_STATE_L0S_DW) if (state & ASPM_STATE_L0S_DW)
upstream |= PCIE_LINK_STATE_L0S; upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
if (state & ASPM_STATE_L1) { if (state & ASPM_STATE_L1) {
upstream |= PCIE_LINK_STATE_L1; upstream |= PCI_EXP_LNKCTL_ASPM_L1;
dwstream |= PCIE_LINK_STATE_L1; dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
} }
/* /*
* Spec 2.0 suggests all functions should be configured the * Spec 2.0 suggests all functions should be configured the
......
drivers/pci/pcie/portdrv_core.c
View file @ 27e1c8ee
...@@ -120,8 +120,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask) ...@@ -120,8 +120,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
* the value in this field indicates which MSI-X Table entry is * the value in this field indicates which MSI-X Table entry is
* used to generate the interrupt message." * used to generate the interrupt message."
*/ */
pos = pci_pcie_cap(dev); pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
if (entry >= nr_entries) if (entry >= nr_entries)
goto Error; goto Error;
......
drivers/pci/probe.c
View file @ 27e1c8ee
...@@ -521,7 +521,7 @@ static unsigned char pcie_link_speed[] = { ...@@ -521,7 +521,7 @@ static unsigned char pcie_link_speed[] = {
void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
{ {
bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
} }
EXPORT_SYMBOL_GPL(pcie_update_link_speed); EXPORT_SYMBOL_GPL(pcie_update_link_speed);
...@@ -579,14 +579,16 @@ static void pci_set_bus_speed(struct pci_bus *bus) ...@@ -579,14 +579,16 @@ static void pci_set_bus_speed(struct pci_bus *bus)
if (pos) { if (pos) {
u16 status; u16 status;
enum pci_bus_speed max; enum pci_bus_speed max;
pci_read_config_word(bridge, pos + 2, &status);
if (status & 0x8000) { pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
&status);
if (status & PCI_X_SSTATUS_533MHZ) {
max = PCI_SPEED_133MHz_PCIX_533; max = PCI_SPEED_133MHz_PCIX_533;
} else if (status & 0x4000) { } else if (status & PCI_X_SSTATUS_266MHZ) {
max = PCI_SPEED_133MHz_PCIX_266; max = PCI_SPEED_133MHz_PCIX_266;
} else if (status & 0x0002) { } else if (status & PCI_X_SSTATUS_133MHZ) {
if (((status >> 12) & 0x3) == 2) { if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
max = PCI_SPEED_133MHz_PCIX_ECC; max = PCI_SPEED_133MHz_PCIX_ECC;
} else { } else {
max = PCI_SPEED_133MHz_PCIX; max = PCI_SPEED_133MHz_PCIX;
...@@ -596,7 +598,8 @@ static void pci_set_bus_speed(struct pci_bus *bus) ...@@ -596,7 +598,8 @@ static void pci_set_bus_speed(struct pci_bus *bus)
} }
bus->max_bus_speed = max; bus->max_bus_speed = max;
bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; bus->cur_bus_speed = pcix_bus_speed[
(status & PCI_X_SSTATUS_FREQ) >> 6];
return; return;
} }
...@@ -607,7 +610,7 @@ static void pci_set_bus_speed(struct pci_bus *bus) ...@@ -607,7 +610,7 @@ static void pci_set_bus_speed(struct pci_bus *bus)
u16 linksta; u16 linksta;
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
pcie_update_link_speed(bus, linksta); pcie_update_link_speed(bus, linksta);
......
include/uapi/linux/pci_regs.h
View file @ 27e1c8ee
...@@ -349,7 +349,7 @@ ...@@ -349,7 +349,7 @@
#define PCI_AF_STATUS_TP 0x01 #define PCI_AF_STATUS_TP 0x01
#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */
/* PCI-X registers */ /* PCI-X registers (Type 0 (non-bridge) devices) */
#define PCI_X_CMD 2 /* Modes & Features */ #define PCI_X_CMD 2 /* Modes & Features */
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
...@@ -389,6 +389,19 @@ ...@@ -389,6 +389,19 @@
#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */
#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */
/* PCI-X registers (Type 1 (bridge) devices) */
#define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */
#define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */
#define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */
#define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */
#define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
#define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */
#define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */
#define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */
#define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */
#define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */
/* PCI Bridge Subsystem ID registers */ /* PCI Bridge Subsystem ID registers */
#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */
...@@ -456,6 +469,8 @@ ...@@ -456,6 +469,8 @@
#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
#define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL 16 /* Link Control */
#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */
#define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */
#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
......
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