Commit 28f6c583 authored by Jerome Brunet's avatar Jerome Brunet Committed by Kevin Hilman

dt-bindings: clk: gxbb: expose i2s output clock gates

Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
parent c1ae3cfa
...@@ -206,16 +206,16 @@ ...@@ -206,16 +206,16 @@
#define CLKID_I2S_SPDIF 35 #define CLKID_I2S_SPDIF 35
/* CLKID_ETH */ /* CLKID_ETH */
#define CLKID_DEMUX 37 #define CLKID_DEMUX 37
#define CLKID_AIU_GLUE 38 /* CLKID_AIU_GLUE */
#define CLKID_IEC958 39 #define CLKID_IEC958 39
#define CLKID_I2S_OUT 40 /* CLKID_I2S_OUT */
#define CLKID_AMCLK 41 #define CLKID_AMCLK 41
#define CLKID_AIFIFO2 42 #define CLKID_AIFIFO2 42
#define CLKID_MIXER 43 #define CLKID_MIXER 43
#define CLKID_MIXER_IFACE 44 /* CLKID_MIXER_IFACE */
#define CLKID_ADC 45 #define CLKID_ADC 45
#define CLKID_BLKMV 46 #define CLKID_BLKMV 46
#define CLKID_AIU 47 /* CLKID_AIU */
#define CLKID_UART1 48 #define CLKID_UART1 48
#define CLKID_G2D 49 #define CLKID_G2D 49
/* CLKID_USB0 */ /* CLKID_USB0 */
...@@ -248,7 +248,7 @@ ...@@ -248,7 +248,7 @@
/* CLKID_GCLK_VENCI_INT0 */ /* CLKID_GCLK_VENCI_INT0 */
#define CLKID_GCLK_VENCI_INT 78 #define CLKID_GCLK_VENCI_INT 78
#define CLKID_DAC_CLK 79 #define CLKID_DAC_CLK 79
#define CLKID_AOCLK_GATE 80 /* CLKID_AOCLK_GATE */
#define CLKID_IEC958_GATE 81 #define CLKID_IEC958_GATE 81
#define CLKID_ENC480P 82 #define CLKID_ENC480P 82
#define CLKID_RNG1 83 #define CLKID_RNG1 83
......
...@@ -16,6 +16,10 @@ ...@@ -16,6 +16,10 @@
#define CLKID_I2C 22 #define CLKID_I2C 22
#define CLKID_SAR_ADC 23 #define CLKID_SAR_ADC 23
#define CLKID_ETH 36 #define CLKID_ETH 36
#define CLKID_AIU_GLUE 38
#define CLKID_I2S_OUT 40
#define CLKID_MIXER_IFACE 44
#define CLKID_AIU 47
#define CLKID_USB0 50 #define CLKID_USB0 50
#define CLKID_USB1 51 #define CLKID_USB1 51
#define CLKID_USB 55 #define CLKID_USB 55
...@@ -24,6 +28,7 @@ ...@@ -24,6 +28,7 @@
#define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_USB0_DDR_BRIDGE 65
#define CLKID_SANA 69 #define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77 #define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AOCLK_GATE 80
#define CLKID_AO_I2C 93 #define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95 #define CLKID_SD_EMMC_B 95
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment