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Commit 29c08460 authored by Russell King's avatar Russell King Committed by Russell King
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Merge branch 'next-s3c' of git://aeryn.fluff.org.uk/bjdooks/linux into devel-stable

parents 9b2616c2 baa28e35
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Documentation/arm/Samsung-S3C24XX/CPUfreq.txt 0 → 100644
View file @ 29c08460
S3C24XX CPUfreq support
=======================
Introduction
------------
The S3C24XX series support a number of power saving systems, such as
the ability to change the core, memory and peripheral operating
frequencies. The core control is exported via the CPUFreq driver
which has a number of different manual or automatic controls over the
rate the core is running at.
There are two forms of the driver depending on the specific CPU and
how the clocks are arranged. The first implementation used as single
PLL to feed the ARM, memory and peripherals via a series of dividers
and muxes and this is the implementation that is documented here. A
newer version where there is a seperate PLL and clock divider for the
ARM core is available as a seperate driver.
Layout
------
The code core manages the CPU specific drivers, any data that they
need to register and the interface to the generic drivers/cpufreq
system. Each CPU registers a driver to control the PLL, clock dividers
and anything else associated with it. Any board that wants to use this
framework needs to supply at least basic details of what is required.
The core registers with drivers/cpufreq at init time if all the data
necessary has been supplied.
CPU support
-----------
The support for each CPU depends on the facilities provided by the
SoC and the driver as each device has different PLL and clock chains
associated with it.
Slow Mode
---------
The SLOW mode where the PLL is turned off altogether and the
system is fed by the external crystal input is currently not
supported.
sysfs
-----
The core code exports extra information via sysfs in the directory
devices/system/cpu/cpu0/arch-freq.
Board Support
-------------
Each board that wants to use the cpufreq code must register some basic
information with the core driver to provide information about what the
board requires and any restrictions being placed on it.
The board needs to supply information about whether it needs the IO bank
timings changing, any maximum frequency limits and information about the
SDRAM refresh rate.
Document Author
---------------
Ben Dooks, Copyright 2009 Simtec Electronics
Licensed under GPLv2
arch/arm/Kconfig
View file @ 29c08460
......@@ -122,6 +122,13 @@ config ARCH_HAS_ILOG2_U32
config ARCH_HAS_ILOG2_U64
bool
config ARCH_HAS_CPUFREQ
bool
help
Internal node to signify that the ARCH has CPUFREQ support
and that the relevant menu configurations are displayed for
it.
config GENERIC_HWEIGHT
bool
default y
......@@ -206,6 +213,7 @@ config ARCH_AAEC2000
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
select ARM_AMBA
select ARCH_HAS_CPUFREQ
select HAVE_CLK
select COMMON_CLKDEV
select ICST525
......@@ -512,6 +520,7 @@ config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
select ARCH_MTD_XIP
select ARCH_HAS_CPUFREQ
select GENERIC_GPIO
select HAVE_CLK
select COMMON_CLKDEV
......@@ -554,6 +563,7 @@ config ARCH_SA1100
select ISA
select ARCH_SPARSEMEM_ENABLE
select ARCH_MTD_XIP
select ARCH_HAS_CPUFREQ
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
......@@ -566,6 +576,7 @@ config ARCH_SA1100
config ARCH_S3C2410
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
select GENERIC_GPIO
select ARCH_HAS_CPUFREQ
select HAVE_CLK
help
Samsung S3C2410X CPU based systems, such as the Simtec Electronics
......@@ -576,9 +587,18 @@ config ARCH_S3C64XX
bool "Samsung S3C64XX"
select GENERIC_GPIO
select HAVE_CLK
select ARCH_HAS_CPUFREQ
help
Samsung S3C64XX series based systems
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
select GENERIC_GPIO
select HAVE_CLK
select CPU_V7
help
Samsung S5PC1XX series based systems
config ARCH_SHARK
bool "Shark"
select CPU_SA110
......@@ -635,6 +655,7 @@ config ARCH_OMAP
select GENERIC_GPIO
select HAVE_CLK
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_CPUFREQ
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
......@@ -688,6 +709,7 @@ source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c64xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
source "arch/arm/plat-s5pc1xx/Kconfig"
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
......@@ -705,6 +727,10 @@ endif
source "arch/arm/plat-stmp3xxx/Kconfig"
if ARCH_S5PC1XX
source "arch/arm/mach-s5pc100/Kconfig"
endif
source "arch/arm/mach-lh7a40x/Kconfig"
source "arch/arm/mach-h720x/Kconfig"
......@@ -1248,7 +1274,7 @@ endmenu
menu "CPU Power Management"
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
if ARCH_HAS_CPUFREQ
source "drivers/cpufreq/Kconfig"
......@@ -1283,6 +1309,52 @@ config CPU_FREQ_S3C64XX
bool "CPUfreq support for Samsung S3C64XX CPUs"
depends on CPU_FREQ && CPU_S3C6410
config CPU_FREQ_S3C
bool
help
Internal configuration node for common cpufreq on Samsung SoC
config CPU_FREQ_S3C24XX
bool "CPUfreq driver for Samsung S3C24XX series CPUs"
depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
select CPU_FREQ_S3C
help
This enables the CPUfreq driver for the Samsung S3C24XX family
of CPUs.
For details, take a look at <file:Documentation/cpu-freq>.
If in doubt, say N.
config CPU_FREQ_S3C24XX_PLL
bool "Support CPUfreq changing of PLL frequency"
depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
help
Compile in support for changing the PLL frequency from the
S3C24XX series CPUfreq driver. The PLL takes time to settle
after a frequency change, so by default it is not enabled.
This also means that the PLL tables for the selected CPU(s) will
be built which may increase the size of the kernel image.
config CPU_FREQ_S3C24XX_DEBUG
bool "Debug CPUfreq Samsung driver core"
depends on CPU_FREQ_S3C24XX
help
Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
config CPU_FREQ_S3C24XX_IODEBUG
bool "Debug CPUfreq Samsung driver IO timing"
depends on CPU_FREQ_S3C24XX
help
Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
config CPU_FREQ_S3C24XX_DEBUGFS
bool "Export debugfs for CPUFreq"
depends on CPU_FREQ_S3C24XX && DEBUG_FS
help
Export status information via debugfs.
endif
source "drivers/cpuidle/Kconfig"
......
arch/arm/Makefile
View file @ 29c08460
......@@ -158,6 +158,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100
machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_STMP378X) := stmp378x
......@@ -177,6 +178,7 @@ plat-$(CONFIG_PLAT_ORION) := orion
plat-$(CONFIG_PLAT_PXA) := pxa
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c
plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
ifeq ($(CONFIG_ARCH_EBSA110),y)
......
arch/arm/configs/s5pc100_defconfig 0 → 100644
View file @ 29c08460
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30
# Wed Jul 1 15:53:07 2009
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_MMU=y
CONFIG_NO_IOPORT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
#
# RCU Subsystem
#
CONFIG_CLASSIC_RCU=y
# CONFIG_TREE_RCU is not set
# CONFIG_PREEMPT_RCU is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_PREEMPT_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
#
# Performance Counters
#
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_COMPAT_BRK=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_CLK=y
#
# GCOV-based kernel profiling
#
# CONFIG_SLOW_WORK is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_BLOCK=y
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_FREEZER is not set
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
CONFIG_ARCH_S5PC1XX=y
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
CONFIG_PLAT_S3C=y
#
# Boot options
#
# CONFIG_S3C_BOOT_ERROR_RESET is not set
CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
#
# Power management
#
CONFIG_S3C_LOWLEVEL_UART_PORT=0
CONFIG_S3C_GPIO_SPACE=0
CONFIG_S3C_GPIO_TRACK=y
CONFIG_S3C_GPIO_PULL_UPDOWN=y
CONFIG_PLAT_S5PC1XX=y
CONFIG_CPU_S5PC100_INIT=y
CONFIG_CPU_S5PC100_CLOCK=y
CONFIG_S5PC100_SETUP_I2C0=y
CONFIG_CPU_S5PC100=y
CONFIG_MACH_SMDKC100=y
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_IFAR=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
CONFIG_ARM_VIC=y
CONFIG_ARM_VIC_NR=2
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_HIGHMEM is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# CPU Power Management
#
# CONFIG_CPU_IDLE is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
# CONFIG_VFP is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_NET is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_MG_DISK is not set
CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_GPIO is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_CONSOLE is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_UARTS=3
# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_DEBUG=y
# CONFIG_HIDRAW is not set
# CONFIG_HID_PID is not set
#
# Special HID drivers
#
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
# Enable Host or Gadget support to see Inventra options
#
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
# CONFIG_USB_GADGET is not set
#
# OTG and related infrastructure
#
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_UNSAFE_RESUME=y
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=y
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PLTFM is not set
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_REGULATOR is not set
# CONFIG_UIO is not set
# CONFIG_STAGING is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_BTRFS_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
CONFIG_GENERIC_ACL=y
#
# Caches
#
# CONFIG_FSCACHE is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_CRAMFS=y
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_NILFS2_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_PI_LIST=y
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_BOOT_TRACER is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_KMEMTRACE is not set
# CONFIG_WORKQUEUE_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARM_UNWIND=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
CONFIG_DEBUG_S3C_PORT=y
CONFIG_DEBUG_S3C_UART=0
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
# CONFIG_BINARY_PRINTF is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y
arch/arm/kernel/irq.c
View file @ 29c08460
......@@ -86,7 +86,7 @@ int show_interrupts(struct seq_file *p, void *v)
unlock:
spin_unlock_irqrestore(&irq_desc[i].lock, flags);
} else if (i == NR_IRQS) {
#ifdef CONFIG_ARCH_ACORN
#ifdef CONFIG_FIQ
show_fiq_list(p, v);
#endif
#ifdef CONFIG_SMP
......
arch/arm/mach-s3c2410/Kconfig
View file @ 29c08460
......@@ -12,6 +12,7 @@ config CPU_S3C2410
select S3C2410_GPIO
select CPU_LLSERIAL_S3C2410
select S3C2410_PM if PM
select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
help
Support for S3C2410 and S3C2410A family from the S3C24XX line
of Samsung Mobile CPUs.
......@@ -45,6 +46,22 @@ config MACH_BAST_IDE
Internal node for machines with an BAST style IDE
interface
# cpu frequency scaling support
config S3C2410_CPUFREQ
bool
depends on CPU_FREQ_S3C24XX && CPU_S3C2410
select S3C2410_CPUFREQ_UTILS
help
CPU Frequency scaling support for S3C2410
config S3C2410_PLLTABLE
bool
depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
default y
help
Select the PLL table for the S3C2410
menu "S3C2410 Machines"
config ARCH_SMDK2410
......@@ -79,6 +96,7 @@ config MACH_N30
config ARCH_BAST
bool "Simtec Electronics BAST (EB2410ITX)"
select CPU_S3C2410
select S3C2410_IOTIMING if S3C2410_CPUFREQ
select PM_SIMTEC if PM
select SIMTEC_NOR
select MACH_BAST_IDE
......
arch/arm/mach-s3c2410/Makefile
View file @ 29c08460
......@@ -15,6 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
obj-$(CONFIG_S3C2410_GPIO) += gpio.o
obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o
obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
# Machine support
......
arch/arm/mach-s3c2410/cpu-freq.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s3c2410/cpu-freq.c
*
* Copyright (c) 2006,2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 CPU Frequency scaling
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/cpu-freq-core.h>
/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
{
u32 clkdiv = 0;
if (cfg->divs.h_divisor == 2)
clkdiv |= S3C2410_CLKDIVN_HDIVN;
if (cfg->divs.p_divisor != cfg->divs.h_divisor)
clkdiv |= S3C2410_CLKDIVN_PDIVN;
__raw_writel(clkdiv, S3C2410_CLKDIVN);
}
static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
{
unsigned long hclk, fclk, pclk;
unsigned int hdiv, pdiv;
unsigned long hclk_max;
fclk = cfg->freq.fclk;
hclk_max = cfg->max.hclk;
cfg->freq.armclk = fclk;
s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
__func__, fclk, hclk_max);
hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
hclk = fclk / hdiv;
if (hclk > cfg->max.hclk) {
s3c_freq_dbg("%s: hclk too big\n", __func__);
return -EINVAL;
}
pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
pclk = hclk / pdiv;
if (pclk > cfg->max.pclk) {
s3c_freq_dbg("%s: pclk too big\n", __func__);
return -EINVAL;
}
pdiv *= hdiv;
/* record the result */
cfg->divs.p_divisor = pdiv;
cfg->divs.h_divisor = hdiv;
return 0 ;
}
static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
.max = {
.fclk = 200000000,
.hclk = 100000000,
.pclk = 50000000,
},
/* transition latency is about 5ms worst-case, so
* set 10ms to be sure */
.latency = 10000000,
.locktime_m = 150,
.locktime_u = 150,
.locktime_bits = 12,
.need_pll = 1,
.name = "s3c2410",
.calc_iotiming = s3c2410_iotiming_calc,
.set_iotiming = s3c2410_iotiming_set,
.get_iotiming = s3c2410_iotiming_get,
.resume_clocks = s3c2410_setup_clocks,
.set_fvco = s3c2410_set_fvco,
.set_refresh = s3c2410_cpufreq_setrefresh,
.set_divs = s3c2410_cpufreq_setdivs,
.calc_divs = s3c2410_cpufreq_calcdivs,
.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
};
static int s3c2410_cpufreq_add(struct sys_device *sysdev)
{
return s3c_cpufreq_register(&s3c2410_cpufreq_info);
}
static struct sysdev_driver s3c2410_cpufreq_driver = {
.add = s3c2410_cpufreq_add,
};
static int __init s3c2410_cpufreq_init(void)
{
return sysdev_driver_register(&s3c2410_sysclass,
&s3c2410_cpufreq_driver);
}
arch_initcall(s3c2410_cpufreq_init);
static int s3c2410a_cpufreq_add(struct sys_device *sysdev)
{
/* alter the maximum freq settings for S3C2410A. If a board knows
* it only has a maximum of 200, then it should register its own
* limits. */
s3c2410_cpufreq_info.max.fclk = 266000000;
s3c2410_cpufreq_info.max.hclk = 133000000;
s3c2410_cpufreq_info.max.pclk = 66500000;
s3c2410_cpufreq_info.name = "s3c2410a";
return s3c2410_cpufreq_add(sysdev);
}
static struct sysdev_driver s3c2410a_cpufreq_driver = {
.add = s3c2410a_cpufreq_add,
};
static int __init s3c2410a_cpufreq_init(void)
{
return sysdev_driver_register(&s3c2410a_sysclass,
&s3c2410a_cpufreq_driver);
}
arch_initcall(s3c2410a_cpufreq_init);
arch/arm/mach-s3c2410/dma.c
View file @ 29c08460
......@@ -164,6 +164,17 @@ static int __init s3c2410_dma_drvinit(void)
}
arch_initcall(s3c2410_dma_drvinit);
static struct sysdev_driver s3c2410a_dma_driver = {
.add = s3c2410_dma_add,
};
static int __init s3c2410a_dma_drvinit(void)
{
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
}
arch_initcall(s3c2410a_dma_drvinit);
#endif
#if defined(CONFIG_CPU_S3C2442)
......
arch/arm/mach-s3c2410/include/mach/gpio-core.h
View file @ 29c08460
......@@ -28,7 +28,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
return NULL;
chip = &s3c24xx_gpios[pin/32];
return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
}
#endif /* __ASM_ARCH_GPIO_CORE_H */
arch/arm/mach-s3c2410/include/mach/irqs.h
View file @ 29c08460
......@@ -164,6 +164,12 @@
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
#ifdef CONFIG_CPU_S3C2440
#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
#else
#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
#endif
/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
#define FIQ_START IRQ_EINT0
......
arch/arm/mach-s3c2410/include/mach/map.h
View file @ 29c08460
......@@ -67,6 +67,13 @@
#define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2443_SZ_HSMMC (256)
/* S3C2412 memory and IO controls */
#define S3C2412_PA_SSMC (0x4F000000)
#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
#define S3C2412_PA_EBI (0x48800000)
#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
/* physical addresses of all the chip-select areas */
#define S3C2410_CS0 (0x00000000)
......@@ -103,5 +110,6 @@
#define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_USBHOST S3C2410_PA_USBHOST
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
#define S3C_PA_NAND S3C24XX_PA_NAND
#endif /* __ASM_ARCH_MAP_H */
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View file @ 29c08460
......@@ -328,13 +328,15 @@
#define S3C2410_GPD8_VD16 (0x02 << 16)
#define S3C2400_GPD8_TOUT3 (0x02 << 16)
#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
#define S3C2410_GPD9_VD17 (0x02 << 18)
#define S3C2400_GPD9_TCLK0 (0x02 << 18)
#define S3C2410_GPD9_MASK (0x03 << 18)
#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
#define S3C2410_GPD10_VD18 (0x02 << 20)
#define S3C2400_GPD10_nWAIT (0x02 << 20)
#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
#define S3C2410_GPD11_VD19 (0x02 << 22)
......
arch/arm/mach-s3c2410/include/mach/regs-mem.h
View file @ 29c08460
......@@ -73,6 +73,16 @@
#define S3C2410_BWSCON_WS7 (1<<30)
#define S3C2410_BWSCON_ST7 (1<<31)
/* accesor functions for getting BANK(n) configuration. (n != 0) */
#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
#define S3C2410_BWSCON_DW8 (0)
#define S3C2410_BWSCON_DW16 (1)
#define S3C2410_BWSCON_DW32 (2)
#define S3C2410_BWSCON_WS (1 << 2)
#define S3C2410_BWSCON_ST (1 << 3)
/* memory set (rom, ram) */
#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
......
arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
View file @ 29c08460
......@@ -14,9 +14,11 @@
#ifndef __ASM_ARM_REGS_S3C2412_MEM
#define __ASM_ARM_REGS_S3C2412_MEM
#ifndef S3C2412_MEMREG
#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#endif
#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
......@@ -26,4 +28,21 @@
#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
/* EBI control registers */
#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
/* SSMC control registers */
#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
#endif /* __ASM_ARM_REGS_S3C2412_MEM */
arch/arm/mach-s3c2410/include/mach/spi.h
View file @ 29c08460
......@@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int enable);
extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
int enable);
#endif /* __ASM_ARCH_SPI_H */
arch/arm/mach-s3c2410/irq.c
View file @ 29c08460
......@@ -39,9 +39,22 @@ static struct sysdev_driver s3c2410_irq_driver = {
.resume = s3c24xx_irq_resume,
};
static int s3c2410_irq_init(void)
static int __init s3c2410_irq_init(void)
{
return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
}
arch_initcall(s3c2410_irq_init);
static struct sysdev_driver s3c2410a_irq_driver = {
.add = s3c2410_irq_add,
.suspend = s3c24xx_irq_suspend,
.resume = s3c24xx_irq_resume,
};
static int __init s3c2410a_irq_init(void)
{
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver);
}
arch_initcall(s3c2410a_irq_init);
arch/arm/mach-s3c2410/mach-bast.c
View file @ 29c08460
......@@ -45,6 +45,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/hwmon.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <mach/fb.h>
......@@ -59,6 +60,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include "usb-simtec.h"
#include "nor-simtec.h"
......@@ -547,7 +549,35 @@ static struct i2c_board_info bast_i2c_devs[] __initdata = {
},
};
static struct s3c_hwmon_pdata bast_hwmon_info = {
/* LCD contrast (0-6.6V) */
.in[0] = &(struct s3c_hwmon_chcfg) {
.name = "lcd-contrast",
.mult = 3300,
.div = 512,
},
/* LED current feedback */
.in[1] = &(struct s3c_hwmon_chcfg) {
.name = "led-feedback",
.mult = 3300,
.div = 1024,
},
/* LCD feedback (0-6.6V) */
.in[2] = &(struct s3c_hwmon_chcfg) {
.name = "lcd-feedback",
.mult = 3300,
.div = 512,
},
/* Vcore (1.8-2.0V), Vref 3.3V */
.in[3] = &(struct s3c_hwmon_chcfg) {
.name = "vcore",
.mult = 3300,
.div = 1024,
},
};
/* Standard BAST devices */
// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
static struct platform_device *bast_devices[] __initdata = {
&s3c_device_usb,
......@@ -556,6 +586,8 @@ static struct platform_device *bast_devices[] __initdata = {
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&s3c_device_adc,
&s3c_device_hwmon,
&bast_device_dm9k,
&bast_device_asix,
&bast_device_axpp,
......@@ -570,6 +602,12 @@ static struct clk *bast_clocks[] __initdata = {
&s3c24xx_uclk,
};
static struct s3c_cpufreq_board __initdata bast_cpufreq = {
.refresh = 7800, /* 7.8usec */
.auto_io = 1,
.need_io = 1,
};
static void __init bast_map_io(void)
{
/* initialise the clocks */
......@@ -588,6 +626,7 @@ static void __init bast_map_io(void)
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_nand.dev.platform_data = &bast_nand_info;
s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);
......@@ -608,6 +647,8 @@ static void __init bast_init(void)
usb_simtec_init();
nor_simtec_init();
s3c_cpufreq_setboard(&bast_cpufreq);
}
MACHINE_START(BAST, "Simtec-BAST")
......
arch/arm/mach-s3c2410/pll.c 0 → 100644
View file @ 29c08460
/* arch/arm/mach-s3c2410/pll.c
*
* Copyright (c) 2006,2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@arm.linux.org.uk>
*
* S3C2410 CPU PLL tables
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sysdev.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
static struct cpufreq_frequency_table pll_vals_12MHz[] = {
{ .frequency = 34000000, .index = PLLVAL(82, 2, 3), },
{ .frequency = 45000000, .index = PLLVAL(82, 1, 3), },
{ .frequency = 51000000, .index = PLLVAL(161, 3, 3), },
{ .frequency = 48000000, .index = PLLVAL(120, 2, 3), },
{ .frequency = 56000000, .index = PLLVAL(142, 2, 3), },
{ .frequency = 68000000, .index = PLLVAL(82, 2, 2), },
{ .frequency = 79000000, .index = PLLVAL(71, 1, 2), },
{ .frequency = 85000000, .index = PLLVAL(105, 2, 2), },
{ .frequency = 90000000, .index = PLLVAL(112, 2, 2), },
{ .frequency = 101000000, .index = PLLVAL(127, 2, 2), },
{ .frequency = 113000000, .index = PLLVAL(105, 1, 2), },
{ .frequency = 118000000, .index = PLLVAL(150, 2, 2), },
{ .frequency = 124000000, .index = PLLVAL(116, 1, 2), },
{ .frequency = 135000000, .index = PLLVAL(82, 2, 1), },
{ .frequency = 147000000, .index = PLLVAL(90, 2, 1), },
{ .frequency = 152000000, .index = PLLVAL(68, 1, 1), },
{ .frequency = 158000000, .index = PLLVAL(71, 1, 1), },
{ .frequency = 170000000, .index = PLLVAL(77, 1, 1), },
{ .frequency = 180000000, .index = PLLVAL(82, 1, 1), },
{ .frequency = 186000000, .index = PLLVAL(85, 1, 1), },
{ .frequency = 192000000, .index = PLLVAL(88, 1, 1), },
{ .frequency = 203000000, .index = PLLVAL(161, 3, 1), },
/* 2410A extras */
{ .frequency = 210000000, .index = PLLVAL(132, 2, 1), },
{ .frequency = 226000000, .index = PLLVAL(105, 1, 1), },
{ .frequency = 266000000, .index = PLLVAL(125, 1, 1), },
{ .frequency = 268000000, .index = PLLVAL(126, 1, 1), },
{ .frequency = 270000000, .index = PLLVAL(127, 1, 1), },
};
static int s3c2410_plls_add(struct sys_device *dev)
{
return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
}
static struct sysdev_driver s3c2410_plls_drv = {
.add = s3c2410_plls_add,
};
static int __init s3c2410_pll_init(void)
{
return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv);
}
arch_initcall(s3c2410_pll_init);
static struct sysdev_driver s3c2410a_plls_drv = {
.add = s3c2410_plls_add,
};
static int __init s3c2410a_pll_init(void)
{
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv);
}
arch_initcall(s3c2410a_pll_init);
arch/arm/mach-s3c2410/pm.c
View file @ 29c08460
......@@ -119,6 +119,18 @@ static int __init s3c2410_pm_drvinit(void)
}
arch_initcall(s3c2410_pm_drvinit);
static struct sysdev_driver s3c2410a_pm_driver = {
.add = s3c2410_pm_add,
.resume = s3c2410_pm_resume,
};
static int __init s3c2410a_pm_drvinit(void)
{
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
}
arch_initcall(s3c2410a_pm_drvinit);
#endif
#if defined(CONFIG_CPU_S3C2440)
......
arch/arm/mach-s3c2410/s3c2410.c
View file @ 29c08460
......@@ -105,17 +105,33 @@ void __init_or_cpufreq s3c2410_setup_clocks(void)
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
/* fake ARMCLK for use with cpufreq, etc. */
static struct clk s3c2410_armclk = {
.name = "armclk",
.parent = &clk_f,
.id = -1,
};
void __init s3c2410_init_clocks(int xtal)
{
s3c24xx_register_baseclocks(xtal);
s3c2410_setup_clocks();
s3c2410_baseclk_add();
s3c24xx_register_clock(&s3c2410_armclk);
}
struct sysdev_class s3c2410_sysclass = {
.name = "s3c2410-core",
};
/* Note, we would have liked to name this s3c2410-core, but we cannot
* register two sysdev_class with the same name.
*/
struct sysdev_class s3c2410a_sysclass = {
.name = "s3c2410a-core",
};
static struct sys_device s3c2410_sysdev = {
.cls = &s3c2410_sysclass,
};
......@@ -133,9 +149,22 @@ static int __init s3c2410_core_init(void)
core_initcall(s3c2410_core_init);
static int __init s3c2410a_core_init(void)
{
return sysdev_class_register(&s3c2410a_sysclass);
}
core_initcall(s3c2410a_core_init);
int __init s3c2410_init(void)
{
printk("S3C2410: Initialising architecture\n");
return sysdev_register(&s3c2410_sysdev);
}
int __init s3c2410a_init(void)
{
s3c2410_sysdev.cls = &s3c2410a_sysclass;
return s3c2410_init();
}
arch/arm/mach-s3c2412/Kconfig
View file @ 29c08460
......@@ -32,6 +32,15 @@ config S3C2412_PM
help
Internal config node to apply S3C2412 power management
# Note, the S3C2412 IOtiming support is in plat-s3c24xx
config S3C2412_CPUFREQ
bool
depends on CPU_FREQ_S3C24XX && CPU_S3C2412
select S3C2412_IOTIMING
default y
help
CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
menu "S3C2412 Machines"
......
arch/arm/mach-s3c2412/Makefile
View file @ 29c08460
......@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_S3C2412) += clock.o
obj-$(CONFIG_CPU_S3C2412) += gpio.o
obj-$(CONFIG_S3C2412_DMA) += dma.o
obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o
obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o
# Machine support
......
arch/arm/mach-s3c2412/cpu-freq.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s3c2412/cpu-freq.c
*
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2412 CPU Frequency scalling
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/regs-clock.h>
#include <mach/regs-s3c2412-mem.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/cpu-freq-core.h>
/* our clock resources. */
static struct clk *xtal;
static struct clk *fclk;
static struct clk *hclk;
static struct clk *armclk;
/* HDIV: 1, 2, 3, 4, 6, 8 */
static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
{
unsigned int hdiv, pdiv, armdiv, dvs;
unsigned long hclk, fclk, armclk, armdiv_clk;
unsigned long hclk_max;
fclk = cfg->freq.fclk;
armclk = cfg->freq.armclk;
hclk_max = cfg->max.hclk;
/* We can't run hclk above armclk as at the best we have to
* have armclk and hclk in dvs mode. */
if (hclk_max > armclk)
hclk_max = armclk;
s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
__func__, fclk, armclk, hclk_max);
s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
__func__, cfg->freq.fclk, cfg->freq.armclk,
cfg->freq.hclk, cfg->freq.pclk);
armdiv = fclk / armclk;
if (armdiv < 1)
armdiv = 1;
if (armdiv > 2)
armdiv = 2;
cfg->divs.arm_divisor = armdiv;
armdiv_clk = fclk / armdiv;
hdiv = armdiv_clk / hclk_max;
if (hdiv < 1)
hdiv = 1;
cfg->freq.hclk = hclk = armdiv_clk / hdiv;
/* set dvs depending on whether we reached armclk or not. */
cfg->divs.dvs = dvs = armclk < armdiv_clk;
/* update the actual armclk we achieved. */
cfg->freq.armclk = dvs ? hclk : armdiv_clk;
s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
__func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
if (hdiv > 4)
goto invalid;
pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
if ((hclk / pdiv) > cfg->max.pclk)
pdiv++;
cfg->freq.pclk = hclk / pdiv;
s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
if (pdiv > 2)
goto invalid;
pdiv *= hdiv;
/* store the result, and then return */
cfg->divs.h_divisor = hdiv * armdiv;
cfg->divs.p_divisor = pdiv * armdiv;
return 0;
invalid:
return -EINVAL;
}
static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
{
unsigned long clkdiv;
unsigned long olddiv;
olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
/* clear off current clock info */
clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
if (cfg->divs.arm_divisor == 2)
clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
if (cfg->divs.p_divisor != cfg->divs.h_divisor)
clkdiv |= S3C2412_CLKDIVN_PDIVN;
s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
__raw_writel(clkdiv, S3C2410_CLKDIVN);
clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
}
static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
{
struct s3c_cpufreq_board *board = cfg->board;
unsigned long refresh;
s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
board->refresh, cfg->freq.hclk);
/* Reduce both the refresh time (in ns) and the frequency (in MHz)
* by 10 each to ensure that we do not overflow 32 bit numbers. This
* should work for HCLK up to 133MHz and refresh period up to 30usec.
*/
refresh = (board->refresh / 10);
refresh *= (cfg->freq.hclk / 100);
refresh /= (1 * 1000 * 1000); /* 10^6 */
s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
__raw_writel(refresh, S3C2412_REFRESH);
}
/* set the default cpu frequency information, based on an 200MHz part
* as we have no other way of detecting the speed rating in software.
*/
static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
.max = {
.fclk = 200000000,
.hclk = 100000000,
.pclk = 50000000,
},
.latency = 5000000, /* 5ms */
.locktime_m = 150,
.locktime_u = 150,
.locktime_bits = 16,
.name = "s3c2412",
.set_refresh = s3c2412_cpufreq_setrefresh,
.set_divs = s3c2412_cpufreq_setdivs,
.calc_divs = s3c2412_cpufreq_calcdivs,
.calc_iotiming = s3c2412_iotiming_calc,
.set_iotiming = s3c2412_iotiming_set,
.get_iotiming = s3c2412_iotiming_get,
.resume_clocks = s3c2412_setup_clocks,
.debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
};
static int s3c2412_cpufreq_add(struct sys_device *sysdev)
{
unsigned long fclk_rate;
hclk = clk_get(NULL, "hclk");
if (IS_ERR(hclk)) {
printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
return -ENOENT;
}
fclk = clk_get(NULL, "fclk");
if (IS_ERR(fclk)) {
printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
goto err_fclk;
}
fclk_rate = clk_get_rate(fclk);
if (fclk_rate > 200000000) {
printk(KERN_INFO
"%s: fclk %ld MHz, assuming 266MHz capable part\n",
__func__, fclk_rate / 1000000);
s3c2412_cpufreq_info.max.fclk = 266000000;
s3c2412_cpufreq_info.max.hclk = 133000000;
s3c2412_cpufreq_info.max.pclk = 66000000;
}
armclk = clk_get(NULL, "armclk");
if (IS_ERR(armclk)) {
printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
goto err_armclk;
}
xtal = clk_get(NULL, "xtal");
if (IS_ERR(xtal)) {
printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
goto err_xtal;
}
return s3c_cpufreq_register(&s3c2412_cpufreq_info);
err_xtal:
clk_put(armclk);
err_armclk:
clk_put(fclk);
err_fclk:
clk_put(hclk);
return -ENOENT;
}
static struct sysdev_driver s3c2412_cpufreq_driver = {
.add = s3c2412_cpufreq_add,
};
static int s3c2412_cpufreq_init(void)
{
return sysdev_driver_register(&s3c2412_sysclass,
&s3c2412_cpufreq_driver);
}
arch_initcall(s3c2412_cpufreq_init);
arch/arm/mach-s3c2412/s3c2412.c
View file @ 29c08460
......@@ -69,6 +69,18 @@ static struct map_desc s3c2412_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
IODESC_ENT(WATCHDOG),
{
.virtual = (unsigned long)S3C2412_VA_SSMC,
.pfn = __phys_to_pfn(S3C2412_PA_SSMC),
.length = SZ_1M,
.type = MT_DEVICE,
},
{
.virtual = (unsigned long)S3C2412_VA_EBI,
.pfn = __phys_to_pfn(S3C2412_PA_EBI),
.length = SZ_1M,
.type = MT_DEVICE,
},
};
/* uart registration process */
......
arch/arm/mach-s3c2440/Kconfig
View file @ 29c08460
......@@ -33,6 +33,7 @@ config MACH_ANUBIS
select PM_SIMTEC if PM
select HAVE_PATA_PLATFORM
select S3C24XX_GPIO_EXTRA64
select S3C2440_XTAL_12000000
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Simtec Electronics ANUBIS
......@@ -44,6 +45,8 @@ config MACH_OSIRIS
select S3C24XX_DCLK
select PM_SIMTEC if PM
select S3C24XX_GPIO_EXTRA128
select S3C2440_XTAL_12000000
select S3C2410_IOTIMING if S3C2440_CPUFREQ
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Simtec IM2440D20 module, also
......@@ -52,6 +55,7 @@ config MACH_OSIRIS
config MACH_RX3715
bool "HP iPAQ rx3715"
select CPU_S3C2440
select S3C2440_XTAL_16934400
select PM_H1940 if PM
help
Say Y here if you are using the HP iPAQ rx3715.
......@@ -59,6 +63,7 @@ config MACH_RX3715
config ARCH_S3C2440
bool "SMDK2440"
select CPU_S3C2440
select S3C2440_XTAL_16934400
select MACH_SMDK
select S3C_DEV_USB_HOST
help
......@@ -67,6 +72,7 @@ config ARCH_S3C2440
config MACH_NEXCODER_2440
bool "NexVision NEXCODER 2440 Light Board"
select CPU_S3C2440
select S3C2440_XTAL_12000000
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
......@@ -75,6 +81,7 @@ config SMDK2440_CPU2440
bool "SMDK2440 with S3C2440 CPU module"
depends on ARCH_S3C2440
default y if ARCH_S3C2440
select S3C2440_XTAL_16934400
select CPU_S3C2440
config MACH_AT2440EVB
......
arch/arm/mach-s3c2440/mach-osiris.c
View file @ 29c08460
......@@ -34,6 +34,7 @@
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
......@@ -351,6 +352,12 @@ static struct clk *osiris_clocks[] __initdata = {
&s3c24xx_uclk,
};
static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
.refresh = 7800, /* refresh period is 7.8usec */
.auto_io = 1,
.need_io = 1,
};
static void __init osiris_map_io(void)
{
unsigned long flags;
......@@ -402,6 +409,8 @@ static void __init osiris_init(void)
s3c_i2c0_set_platdata(NULL);
s3c_cpufreq_setboard(&osiris_cpufreq);
i2c_register_board_info(0, osiris_i2c_devs,
ARRAY_SIZE(osiris_i2c_devs));
......
arch/arm/mach-s3c24a0/include/mach/map.h
View file @ 29c08460
......@@ -81,5 +81,6 @@
#define S3C_PA_UART S3C24A0_PA_UART
#define S3C_PA_IIC S3C24A0_PA_IIC
#define S3C_PA_NAND S3C24XX_PA_NAND
#endif /* __ASM_ARCH_24A0_MAP_H */
arch/arm/mach-s3c6400/include/mach/map.h
View file @ 29c08460
......@@ -38,18 +38,21 @@
#define S3C_VA_UART2 S3C_VA_UARTx(2)
#define S3C_VA_UART3 S3C_VA_UARTx(3)
#define S3C64XX_PA_NAND (0x70200000)
#define S3C64XX_PA_FB (0x77100000)
#define S3C64XX_PA_USB_HSOTG (0x7C000000)
#define S3C64XX_PA_WATCHDOG (0x7E004000)
#define S3C64XX_PA_SYSCON (0x7E00F000)
#define S3C64XX_PA_AC97 (0x7F001000)
#define S3C64XX_PA_IIS0 (0x7F002000)
#define S3C64XX_PA_IIS1 (0x7F003000)
#define S3C64XX_PA_TIMER (0x7F006000)
#define S3C64XX_PA_IIC0 (0x7F004000)
#define S3C64XX_PA_IISV4 (0x7F00D000)
#define S3C64XX_PA_IIC1 (0x7F00F000)
#define S3C64XX_PA_GPIO (0x7F008000)
#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000)
#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
#define S3C64XX_SZ_GPIO SZ_4K
#define S3C64XX_PA_SDRAM (0x50000000)
......@@ -57,7 +60,7 @@
#define S3C64XX_PA_VIC1 (0x71300000)
#define S3C64XX_PA_MODEM (0x74108000)
#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
#define S3C64XX_PA_USBHOST (0x74300000)
......@@ -72,6 +75,7 @@
#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
#define S3C_PA_IIC S3C64XX_PA_IIC0
#define S3C_PA_IIC1 S3C64XX_PA_IIC1
#define S3C_PA_NAND S3C64XX_PA_NAND
#define S3C_PA_FB S3C64XX_PA_FB
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
......
arch/arm/mach-s3c6400/s3c6400.c
View file @ 29c08460
......@@ -48,6 +48,8 @@ void __init s3c6400_map_io(void)
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_device_nand.name = "s3c6400-nand";
}
void __init s3c6400_init_clocks(int xtal)
......
arch/arm/mach-s3c6410/Kconfig
View file @ 29c08460
......@@ -97,3 +97,13 @@ config MACH_NCP
select S3C64XX_SETUP_I2C1
help
Machine support for the Samsung NCP
config MACH_HMT
bool "Airgoo HMT"
select CPU_S3C6410
select S3C_DEV_FB
select S3C_DEV_USB_HOST
select S3C64XX_SETUP_FB_24BPP
select HAVE_PWM
help
Machine support for the Airgoo HMT
arch/arm/mach-s3c6410/Makefile
View file @ 29c08460
......@@ -23,5 +23,4 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
obj-$(CONFIG_MACH_HMT) += mach-hmt.o
arch/arm/mach-s3c6410/cpu.c
View file @ 29c08460
......@@ -62,6 +62,8 @@ void __init s3c6410_map_io(void)
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_device_nand.name = "s3c6400-nand";
}
void __init s3c6410_init_clocks(int xtal)
......
arch/arm/mach-s3c6410/mach-hmt.c 0 → 100644
View file @ 29c08460
/* mach-hmt.c - Platform code for Airgoo HMT
*
* Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/leds.h>
#include <linux/pwm_backlight.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/nand.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
};
static int hmt_bl_init(struct device *dev)
{
int ret;
ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable");
if (!ret)
ret = gpio_direction_output(S3C64XX_GPB(4), 0);
return ret;
}
static int hmt_bl_notify(int brightness)
{
/*
* translate from CIELUV/CIELAB L*->brightness, E.G. from
* perceived luminance to light output. Assumes range 0..25600
*/
if (brightness < 0x800) {
/* Y = Yn * L / 903.3 */
brightness = (100*256 * brightness + 231245/2) / 231245;
} else {
/* Y = Yn * ((L + 16) / 116 )^3 */
int t = (brightness*4 + 16*1024 + 58)/116;
brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000);
}
gpio_set_value(S3C64XX_GPB(4), brightness);
return brightness;
}
static void hmt_bl_exit(struct device *dev)
{
gpio_free(S3C64XX_GPB(4));
}
static struct platform_pwm_backlight_data hmt_backlight_data = {
.pwm_id = 1,
.max_brightness = 100 * 256,
.dft_brightness = 40 * 256,
.pwm_period_ns = 1000000000 / (100 * 256 * 20),
.init = hmt_bl_init,
.notify = hmt_bl_notify,
.exit = hmt_bl_exit,
};
static struct platform_device hmt_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &s3c_device_timer[1].dev,
.platform_data = &hmt_backlight_data,
},
};
static struct s3c_fb_pd_win hmt_fb_win0 = {
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
};
/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.win[0] = &hmt_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
static struct mtd_partition hmt_nand_part[] = {
[0] = {
.name = "uboot",
.size = SZ_512K,
.offset = 0,
},
[1] = {
.name = "uboot-env1",
.size = SZ_256K,
.offset = SZ_512K,
},
[2] = {
.name = "uboot-env2",
.size = SZ_256K,
.offset = SZ_512K + SZ_256K,
},
[3] = {
.name = "kernel",
.size = SZ_2M,
.offset = SZ_1M,
},
[4] = {
.name = "rootfs",
.size = MTDPART_SIZ_FULL,
.offset = SZ_1M + SZ_2M,
},
};
static struct s3c2410_nand_set hmt_nand_sets[] = {
[0] = {
.name = "nand",
.nr_chips = 1,
.nr_partitions = ARRAY_SIZE(hmt_nand_part),
.partitions = hmt_nand_part,
},
};
static struct s3c2410_platform_nand hmt_nand_info = {
.tacls = 25,
.twrph0 = 55,
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(hmt_nand_sets),
.sets = hmt_nand_sets,
};
static struct gpio_led hmt_leds[] = {
{ /* left function keys */
.name = "left:blue",
.gpio = S3C64XX_GPO(12),
.default_trigger = "default-on",
},
{ /* right function keys - red */
.name = "right:red",
.gpio = S3C64XX_GPO(13),
},
{ /* right function keys - green */
.name = "right:green",
.gpio = S3C64XX_GPO(14),
},
{ /* right function keys - blue */
.name = "right:blue",
.gpio = S3C64XX_GPO(15),
.default_trigger = "default-on",
},
};
static struct gpio_led_platform_data hmt_led_data = {
.num_leds = ARRAY_SIZE(hmt_leds),
.leds = hmt_leds,
};
static struct platform_device hmt_leds_device = {
.name = "leds-gpio",
.id = -1,
.dev.platform_data = &hmt_led_data,
};
static struct map_desc hmt_iodesc[] = {};
static struct platform_device *hmt_devices[] __initdata = {
&s3c_device_i2c0,
&s3c_device_nand,
&s3c_device_fb,
&s3c_device_usb,
&s3c_device_timer[1],
&hmt_backlight_device,
&hmt_leds_device,
};
static void __init hmt_map_io(void)
{
s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
}
static void __init hmt_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_fb_set_platdata(&hmt_lcd_pdata);
s3c_device_nand.dev.platform_data = &hmt_nand_info;
gpio_request(S3C64XX_GPC(7), "usb power");
gpio_direction_output(S3C64XX_GPC(7), 0);
gpio_request(S3C64XX_GPM(0), "usb power");
gpio_direction_output(S3C64XX_GPM(0), 1);
gpio_request(S3C64XX_GPK(7), "usb power");
gpio_direction_output(S3C64XX_GPK(7), 1);
gpio_request(S3C64XX_GPF(13), "usb power");
gpio_direction_output(S3C64XX_GPF(13), 1);
platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices));
}
MACHINE_START(HMT, "Airgoo-HMT")
/* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6410_init_irq,
.map_io = hmt_map_io,
.init_machine = hmt_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/mach-s3c6410/mach-ncp.c
View file @ 29c08460
......@@ -79,7 +79,7 @@ static struct platform_device *ncp_devices[] __initdata = {
&s3c_device_i2c0,
};
struct map_desc ncp_iodesc[] = {};
static struct map_desc ncp_iodesc[] __initdata = {};
static void __init ncp_map_io(void)
{
......
arch/arm/mach-s3c6410/mach-smdk6410.c
View file @ 29c08460
......@@ -65,16 +65,30 @@ static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
};
......
arch/arm/mach-s5pc100/Kconfig 0 → 100644
View file @ 29c08460
# arch/arm/mach-s5pc100/Kconfig
#
# Copyright 2009 Samsung Electronics Co.
# Byungho Min <bhmin@samsung.com>
#
# Licensed under GPLv2
# Configuration options for the S5PC100 CPU
config CPU_S5PC100
bool
select CPU_S5PC100_INIT
select CPU_S5PC100_CLOCK
help
Enable S5PC100 CPU support
config MACH_SMDKC100
bool "SMDKC100"
select CPU_S5PC100
select S5PC1XX_SETUP_I2C1
help
Machine support for the Samsung SMDKC100
arch/arm/mach-s5pc100/Makefile 0 → 100644
View file @ 29c08460
# arch/arm/mach-s5pc100/Makefile
#
# Copyright 2009 Samsung Electronics Co.
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S5PC100 system
obj-$(CONFIG_CPU_S5PC100) += cpu.o
# machine support
obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
arch/arm/mach-s5pc100/Makefile.boot 0 → 100644
View file @ 29c08460
zreladdr-y := 0x20008000
params_phys-y := 0x20000100
arch/arm/mach-s5pc100/cpu.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/cpu.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Based on mach-s3c6410/cpu.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/s5pc100.h>
/* Initial IO mappings */
static struct map_desc s5pc100_iodesc[] __initdata = {
};
/* s5pc100_map_io
*
* register the standard cpu IO areas
*/
void __init s5pc100_map_io(void)
{
iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
/* initialise device information early */
}
void __init s5pc100_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5pc1xx_register_clocks();
s5pc100_register_clocks();
s5pc100_setup_clocks();
}
void __init s5pc100_init_irq(void)
{
u32 vic_valid[] = {~0, ~0, ~0};
/* VIC0, VIC1, and VIC2 are fully populated. */
s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid));
}
struct sysdev_class s5pc100_sysclass = {
.name = "s5pc100-core",
};
static struct sys_device s5pc100_sysdev = {
.cls = &s5pc100_sysclass,
};
static int __init s5pc100_core_init(void)
{
return sysdev_class_register(&s5pc100_sysclass);
}
core_initcall(s5pc100_core_init);
int __init s5pc100_init(void)
{
printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
return sysdev_register(&s5pc100_sysdev);
}
arch/arm/mach-s5pc100/include/mach/debug-macro.S 0 → 100644
View file @ 29c08460
/* arch/arm/mach-s5pc100/include/mach/debug-macro.S
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
*
* Based on mach-s3c6400/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
* mapping the head code makes. We keep the UART virtual address
* aligned and add in the offset when we load the value here.
*/
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C_PA_UART
ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
.endm
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>
arch/arm/mach-s5pc100/include/mach/entry-macro.S 0 → 100644
View file @ 29c08460
/* arch/arm/mach-s5pc100/include/mach/entry-macro.S
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Based on mach-s3c6400/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for the Samsung S5PC1XX series
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =S3C_VA_VIC0
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check the vic0
mov \irqnr, # S3C_IRQ_OFFSET + 31
ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
teq \irqstat, #0
@ otherwise try vic1
addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
@ otherwise try vic2
addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm
arch/arm/mach-s5pc100/include/mach/gpio-core.h 0 → 100644
View file @ 29c08460
/* arch/arm/mach-s5pc100/include/mach/gpio-core.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - GPIO core support
*
* Based on mach-s3c6400/include/mach/gpio-core.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
/* currently we just include the platform support */
#include <plat/gpio-core.h>
#endif /* __ASM_ARCH_GPIO_CORE_H */
arch/arm/mach-s5pc100/include/mach/gpio.h 0 → 100644
View file @ 29c08460
/* arch/arm/mach-s5pc100/include/mach/gpio.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - GPIO lib support
*
* Base on mach-s3c6400/include/mach/gpio.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S5PC1XX_GPIO_A0_NR (8)
#define S5PC1XX_GPIO_A1_NR (5)
#define S5PC1XX_GPIO_B_NR (8)
#define S5PC1XX_GPIO_C_NR (5)
#define S5PC1XX_GPIO_D_NR (7)
#define S5PC1XX_GPIO_E0_NR (8)
#define S5PC1XX_GPIO_E1_NR (6)
#define S5PC1XX_GPIO_F0_NR (8)
#define S5PC1XX_GPIO_F1_NR (8)
#define S5PC1XX_GPIO_F2_NR (8)
#define S5PC1XX_GPIO_F3_NR (4)
#define S5PC1XX_GPIO_G0_NR (8)
#define S5PC1XX_GPIO_G1_NR (3)
#define S5PC1XX_GPIO_G2_NR (7)
#define S5PC1XX_GPIO_G3_NR (7)
#define S5PC1XX_GPIO_H0_NR (8)
#define S5PC1XX_GPIO_H1_NR (8)
#define S5PC1XX_GPIO_H2_NR (8)
#define S5PC1XX_GPIO_H3_NR (8)
#define S5PC1XX_GPIO_I_NR (8)
#define S5PC1XX_GPIO_J0_NR (8)
#define S5PC1XX_GPIO_J1_NR (5)
#define S5PC1XX_GPIO_J2_NR (8)
#define S5PC1XX_GPIO_J3_NR (8)
#define S5PC1XX_GPIO_J4_NR (4)
#define S5PC1XX_GPIO_K0_NR (8)
#define S5PC1XX_GPIO_K1_NR (6)
#define S5PC1XX_GPIO_K2_NR (8)
#define S5PC1XX_GPIO_K3_NR (8)
#define S5PC1XX_GPIO_MP00_NR (8)
#define S5PC1XX_GPIO_MP01_NR (8)
#define S5PC1XX_GPIO_MP02_NR (8)
#define S5PC1XX_GPIO_MP03_NR (8)
#define S5PC1XX_GPIO_MP04_NR (5)
/* GPIO bank numbes */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S5PC1XX_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s3c_gpio_number {
S5PC1XX_GPIO_A0_START = 0,
S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0),
S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1),
S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B),
S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C),
S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D),
S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0),
S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1),
S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0),
S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1),
S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2),
S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3),
S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0),
S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1),
S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2),
S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3),
S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0),
S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1),
S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2),
S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3),
S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I),
S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0),
S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1),
S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2),
S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3),
S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4),
S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0),
S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1),
S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2),
S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3),
S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00),
S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01),
S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02),
S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03),
};
/* S5PC1XX GPIO number definitions. */
#define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr))
#define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr))
#define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr))
#define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr))
#define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr))
#define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr))
#define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr))
#define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr))
#define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr))
#define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr))
#define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr))
#define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr))
#define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr))
#define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr))
#define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr))
#define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr))
#define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr))
#define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr))
#define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr))
#define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr))
#define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr))
#define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr))
#define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr))
#define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr))
#define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr))
#define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr))
#define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr))
#define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr))
#define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr))
#define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr))
#define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr))
#define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr))
#define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr))
#define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr))
/* the end of the S5PC1XX specific gpios */
#define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
#define S3C_GPIO_END S5PC1XX_GPIO_END
/* define the number of gpios we need to the one after the MP04() range */
#define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
#include <asm-generic/gpio.h>
arch/arm/mach-s5pc100/include/mach/hardware.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - Hardware support
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_HARDWARE_H */
arch/arm/mach-s5pc100/include/mach/irqs.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - IRQ definitions
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s5pc100/include/mach/map.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/include/mach/map.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Based on mach-s3c6400/include/mach/map.h
*
* S5PC1XX - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
/* Chip ID */
#define S5PC100_PA_CHIPID (0xE0000000)
#define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID
#define S5PC1XX_VA_CHIPID S3C_VA_SYS
/* System */
#define S5PC100_PA_SYS (0xE0100000)
#define S5PC100_PA_CLK (S5PC100_PA_SYS + 0x0)
#define S5PC100_PA_PWR (S5PC100_PA_SYS + 0x8000)
#define S5PC1XX_PA_CLK S5PC100_PA_CLK
#define S5PC1XX_PA_PWR S5PC100_PA_PWR
#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000)
#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000)
/* Interrupt */
#define S5PC100_PA_VIC (0xE4000000)
#define S5PC100_VA_VIC S3C_VA_IRQ
#define S5PC100_PA_VIC_OFFSET 0x100000
#define S5PC100_VA_VIC_OFFSET 0x10000
#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
/* Timer */
#define S5PC100_PA_TIMER (0xEA000000)
#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER
#define S5PC1XX_VA_TIMER S3C_VA_TIMER
/* UART */
#define S5PC100_PA_UART (0xEC000000)
#define S5PC1XX_PA_UART S5PC100_PA_UART
#define S5PC1XX_VA_UART S3C_VA_UART
/* IIC */
#define S5PC100_PA_IIC (0xEC100000)
/* ETC */
#define S5PC100_PA_SDRAM (0x20000000)
/* compatibility defines. */
#define S3C_PA_UART S5PC100_PA_UART
#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0)
#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400)
#define S3C_PA_UART2 (S5PC100_PA_UART + 0x800)
#define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00)
#define S3C_VA_UART0 (S3C_VA_UART + 0x0)
#define S3C_VA_UART1 (S3C_VA_UART + 0x400)
#define S3C_VA_UART2 (S3C_VA_UART + 0x800)
#define S3C_VA_UART3 (S3C_VA_UART + 0xC00)
#define S3C_UART_OFFSET 0x400
#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0)
#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000)
#define S3C_PA_IIC S5PC100_PA_IIC
#endif /* __ASM_ARCH_C100_MAP_H */
arch/arm/mach-s5pc100/include/mach/memory.h 0 → 100644
View file @ 29c08460
/* arch/arm/mach-s5pc100/include/mach/memory.h
*
* Copyright 2008 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Based on mach-s3c6400/include/mach/memory.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x20000000)
#endif
arch/arm/mach-s5pc100/include/mach/pwm-clock.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - pwm clock and timer support
*
* Based on mach-s3c6400/include/mach/pwm-clock.h
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
arch/arm/mach-s5pc100/include/mach/regs-irq.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <mach/map.h>
#include <asm/hardware/vic.h>
/* interrupt controller */
#define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0))
#define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1))
#define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2))
#endif /* __ASM_ARCH_REGS_IRQ_H */
arch/arm/mach-s5pc100/include/mach/system.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/include/mach/system.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX - system implementation
*
* Based on mach-s3c6400/include/mach/system.h
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__
static void arch_idle(void)
{
/* nothing here yet */
}
static void arch_reset(char mode, const char *cmd)
{
/* nothing here yet */
}
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s5pc100/include/mach/tick.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/include/mach/tick.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S3C64XX - Timer tick support definitions
*
* Based on mach-s3c6400/include/mach/tick.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TICK_H
#define __ASM_ARCH_TICK_H __FILE__
/* note, the timer interrutps turn up in 2 places, the vic and then
* the timer block. We take the VIC as the base at the moment.
*/
static inline u32 s3c24xx_ostimer_pending(void)
{
u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0));
}
#define TICK_MAX (0xffffffff)
#endif /* __ASM_ARCH_TICK_H */
arch/arm/mach-s5pc100/include/mach/uncompress.h 0 → 100644
View file @ 29c08460
/* arch/arm/mach-s5pc100/include/mach/uncompress.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - uncompress code
*
* Based on mach-s3c6400/include/mach/uncompress.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
#include <plat/uncompress.h>
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
fifo_mask = S3C2440_UFSTAT_TXMASK;
fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */
arch/arm/mach-s5pc100/mach-smdkc100.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c
*
* Copyright 2009 Samsung Electronics Co.
* Author: Byungho Min <bhmin@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/s5pc100.h>
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
};
static struct map_desc smdkc100_iodesc[] = {};
static struct platform_device *smdkc100_devices[] __initdata = {
};
static void __init smdkc100_map_io(void)
{
s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
}
static void __init smdkc100_machine_init(void)
{
platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
}
MACHINE_START(SMDKC100, "SMDKC100")
/* Maintainer: Byungho Min <bhmin@samsung.com> */
.phys_io = S5PC1XX_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S5PC100_PA_SDRAM + 0x100,
.init_irq = s5pc100_init_irq,
.map_io = smdkc100_map_io,
.init_machine = smdkc100_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/plat-s3c/Kconfig
View file @ 29c08460
......@@ -198,4 +198,9 @@ config S3C_DEV_USB_HSOTG
help
Compile in platform device definition for USB high-speed OtG
config S3C_DEV_NAND
bool
help
Compile in platform device definition for NAND controller
endif
arch/arm/plat-s3c/Makefile
View file @ 29c08460
......@@ -28,13 +28,17 @@ obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += pm-gpio.o
obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
# PWM support
obj-$(CONFIG_HAVE_PWM) += pwm.o
# devices
obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_SND_S3C64XX_SOC_I2S) += dev-audio.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o
arch/arm/plat-s3c/dev-nand.c 0 → 100644
View file @ 29c08460
/*
* S3C series device definition for nand device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/devs.h>
static struct resource s3c_nand_resource[] = {
[0] = {
.start = S3C_PA_NAND,
.end = S3C_PA_NAND + SZ_1M,
.flags = IORESOURCE_MEM,
}
};
struct platform_device s3c_device_nand = {
.name = "s3c2410-nand",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_nand_resource),
.resource = s3c_nand_resource,
};
EXPORT_SYMBOL(s3c_device_nand);
arch/arm/plat-s3c/include/plat/adc.h
View file @ 29c08460
......@@ -19,10 +19,14 @@ struct s3c_adc_client;
extern int s3c_adc_start(struct s3c_adc_client *client,
unsigned int channel, unsigned int nr_samples);
extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch);
extern struct s3c_adc_client *
s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned selected),
void (*conv)(unsigned d0, unsigned d1,
void (*select)(struct s3c_adc_client *client,
unsigned selected),
void (*conv)(struct s3c_adc_client *client,
unsigned d0, unsigned d1,
unsigned *samples_left),
unsigned int is_ts);
......
arch/arm/plat-s3c/include/plat/cpu-freq.h
View file @ 29c08460
......@@ -17,6 +17,21 @@ struct s3c_cpufreq_info;
struct s3c_cpufreq_board;
struct s3c_iotimings;
/**
* struct s3c_freq - frequency information (mainly for core drivers)
* @fclk: The FCLK frequency in Hz.
* @armclk: The ARMCLK frequency in Hz.
* @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
* @hclk: The HCLK frequency in Hz.
* @pclk: The PCLK frequency in Hz.
*
* This contains the frequency information about the current configuration
* mainly for the core drivers to ensure we do not end up passing about
* a large number of parameters.
*
* The @hclk_tns field is a useful cache for the parts of the drivers that
* need to calculate IO timings and suchlike.
*/
struct s3c_freq {
unsigned long fclk;
unsigned long armclk;
......@@ -25,48 +40,84 @@ struct s3c_freq {
unsigned long pclk;
};
/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
/**
* struct s3c_cpufreq_freqs - s3c cpufreq notification information.
* @freqs: The cpufreq setting information.
* @old: The old clock settings.
* @new: The new clock settings.
* @pll_changing: Set if the PLL is changing.
*
* Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
* notification can use this information that is not provided by just
* having the core frequency alone.
*
* The pll_changing flag is used to indicate if the PLL itself is
* being set during this change. This is important as the clocks
* will temporarily be set to the XTAL clock during this time, so
* drivers may want to close down their output during this time.
*
* Note, this is not being used by any current drivers and therefore
* may be removed in the future.
*/
struct s3c_cpufreq_freqs {
struct cpufreq_freqs freqs;
struct s3c_freq old;
struct s3c_freq new;
unsigned int pll_changing:1;
};
#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
/**
* struct s3c_clkdivs - clock divisor information
* @p_divisor: Divisor from FCLK to PCLK.
* @h_divisor: Divisor from FCLK to HCLK.
* @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
* @dvs: Non-zero if using DVS mode for ARMCLK.
*
* Divisor settings for the core clocks.
*/
struct s3c_clkdivs {
int p_divisor; /* fclk / pclk */
int h_divisor; /* fclk / hclk */
int arm_divisor; /* not all cpus have this. */
unsigned char dvs; /* using dvs mode to arm. */
int p_divisor;
int h_divisor;
int arm_divisor;
unsigned char dvs;
};
#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
/**
* struct s3c_pllval - PLL value entry.
* @freq: The frequency for this entry in Hz.
* @pll_reg: The PLL register setting for this PLL value.
*/
struct s3c_pllval {
unsigned long freq;
unsigned long pll_reg;
};
struct s3c_cpufreq_config {
struct s3c_freq freq;
struct s3c_pllval pll;
struct s3c_clkdivs divs;
struct s3c_cpufreq_info *info; /* for core, not drivers */
struct s3c_cpufreq_board *board;
};
/* s3c_cpufreq_board
/**
* struct s3c_cpufreq_board - per-board cpu frequency informatin
* @refresh: The SDRAM refresh period in nanoseconds.
* @auto_io: Set if the IO timing settings should be generated from the
* initialisation time hardware registers.
* @need_io: Set if the board has external IO on any of the chipselect
* lines that will require the hardware timing registers to be
* updated on a clock change.
* @max: The maxium frequency limits for the system. Any field that
* is left at zero will use the CPU's settings.
*
* This contains the board specific settings that affect how the CPU
* drivers chose settings. These include the memory refresh and IO
* timing information.
*
* per-board configuraton information, such as memory refresh and
* how to initialise IO timings.
* Registration depends on the driver being used, the ARMCLK only
* implementation does not currently need this but the older style
* driver requires this to be available.
*/
struct s3c_cpufreq_board {
unsigned int refresh; /* refresh period in ns */
unsigned int refresh;
unsigned int auto_io:1; /* automatically init io timings. */
unsigned int need_io:1; /* set if needs io timing support. */
......
arch/arm/plat-s3c/include/plat/cpu.h
View file @ 29c08460
......@@ -65,6 +65,7 @@ extern struct sys_timer s3c24xx_timer;
/* system device classes */
extern struct sysdev_class s3c2410_sysclass;
extern struct sysdev_class s3c2410a_sysclass;
extern struct sysdev_class s3c2412_sysclass;
extern struct sysdev_class s3c2440_sysclass;
extern struct sysdev_class s3c2442_sysclass;
......
arch/arm/plat-s3c/include/plat/devs.h
View file @ 29c08460
......@@ -46,6 +46,8 @@ extern struct platform_device s3c_device_hsmmc2;
extern struct platform_device s3c_device_spi0;
extern struct platform_device s3c_device_spi1;
extern struct platform_device s3c_device_hwmon;
extern struct platform_device s3c_device_nand;
extern struct platform_device s3c_device_usbgadget;
......@@ -56,5 +58,6 @@ extern struct platform_device s3c_device_usb_hsotg;
#ifdef CONFIG_CPU_S3C2440
extern struct platform_device s3c_device_camif;
extern struct platform_device s3c_device_ac97;
#endif
arch/arm/plat-s3c/include/plat/hwmon.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
*
* Copyright 2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C - HWMon interface for ADC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_ADC_HWMON_H
#define __ASM_ARCH_ADC_HWMON_H __FILE__
/**
* s3c_hwmon_chcfg - channel configuration
* @name: The name to give this channel.
* @mult: Multiply the ADC value read by this.
* @div: Divide the value from the ADC by this.
*
* The value read from the ADC is converted to a value that
* hwmon expects (mV) by result = (value_read * @mult) / @div.
*/
struct s3c_hwmon_chcfg {
const char *name;
unsigned int mult;
unsigned int div;
};
/**
* s3c_hwmon_pdata - HWMON platform data
* @in: One configuration for each possible channel used.
*/
struct s3c_hwmon_pdata {
struct s3c_hwmon_chcfg *in[8];
};
#endif /* __ASM_ARCH_ADC_HWMON_H */
arch/arm/plat-s3c/include/plat/map-base.h
View file @ 29c08460
......@@ -32,9 +32,15 @@
#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */
#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
/* This is used for the CPU specific mappings that may be needed, so that
* they do not need to directly used S3C_ADDR() and thus make it easier to
* modify the space for mapping.
*/
#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
#endif /* __ASM_PLAT_MAP_H */
arch/arm/plat-s3c24xx/pwm.c → arch/arm/plat-s3c/pwm.c
View file @ 29c08460
/* arch/arm/plat-s3c24xx/pwm.c
/* arch/arm/plat-s3c/pwm.c
*
* Copyright (c) 2007 Ben Dooks
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
*
* S3C24XX PWM device core
* S3C series PWM device core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -20,6 +20,7 @@
#include <linux/pwm.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <plat/devs.h>
#include <plat/regs-timer.h>
......
arch/arm/plat-s3c24xx/Kconfig
View file @ 29c08460
......@@ -10,6 +10,7 @@ config PLAT_S3C24XX
default y
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_DEVICE_NAND
help
Base platform code for any Samsung S3C24XX device
......@@ -34,6 +35,40 @@ config CPU_S3C244X
help
Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
config S3C2440_CPUFREQ
bool "S3C2440/S3C2442 CPU Frequency scaling support"
depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
select S3C2410_CPUFREQ_UTILS
default y
help
CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
config S3C2440_XTAL_12000000
bool
help
Indicate that the build needs to support 12MHz system
crystal.
config S3C2440_XTAL_16934400
bool
help
Indicate that the build needs to support 16.9344MHz system
crystal.
config S3C2440_PLL_12000000
bool
depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
default y if CPU_FREQ_S3C24XX_PLL
help
PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
config S3C2440_PLL_16934400
bool
depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
default y if CPU_FREQ_S3C24XX_PLL
help
PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
config S3C24XX_PWM
bool "PWM device support"
select HAVE_PWM
......@@ -105,8 +140,39 @@ config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
SPI GPIO configuration code for BUS 1 when connected to
GPG5, GPG6 and GPG7.
config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10
bool
help
SPI GPIO configuration code for BUS 1 when connected to
GPD8, GPD9 and GPD10.
# common code for s3c24xx based machines, such as the SMDKs.
# cpu frequency items common between s3c2410 and s3c2440/s3c2442
config S3C2410_IOTIMING
bool
depends on CPU_FREQ_S3C24XX
help
Internal node to select io timing code that is common to the s3c2410
and s3c2440/s3c2442 cpu frequency support.
config S3C2410_CPUFREQ_UTILS
bool
depends on CPU_FREQ_S3C24XX
help
Internal node to select timing code that is common to the s3c2410
and s3c2440/s3c244 cpu frequency support.
# cpu frequency support common to s3c2412, s3c2413 and s3c2442
config S3C2412_IOTIMING
bool
depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
help
Intel node to select io timing code that is common to the s3c2412
and the s3c2443.
config MACH_SMDK
bool
help
......
arch/arm/plat-s3c24xx/Makefile
View file @ 29c08460
......@@ -20,19 +20,28 @@ obj-y += gpiolib.o
obj-y += clock.o
obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o
obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
# Architecture dependant builds
obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o
obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += irq-pm.o
obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_S3C24XX_PWM) += pwm.o
obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
obj-$(CONFIG_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C24XX_ADC) += adc.o
obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
# device specific setup and/or initialisation
obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
......@@ -41,6 +50,7 @@ obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o
obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10) += spi-bus1-gpd8_9_10.o
# machine common support
......
arch/arm/plat-s3c24xx/adc.c
View file @ 29c08460
......@@ -39,13 +39,16 @@
struct s3c_adc_client {
struct platform_device *pdev;
struct list_head pend;
wait_queue_head_t *wait;
unsigned int nr_samples;
int result;
unsigned char is_ts;
unsigned char channel;
void (*select_cb)(unsigned selected);
void (*convert_cb)(unsigned val1, unsigned val2,
void (*select_cb)(struct s3c_adc_client *c, unsigned selected);
void (*convert_cb)(struct s3c_adc_client *c,
unsigned val1, unsigned val2,
unsigned *samples_left);
};
......@@ -81,7 +84,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
{
unsigned con = readl(adc->regs + S3C2410_ADCCON);
client->select_cb(1);
client->select_cb(client, 1);
con &= ~S3C2410_ADCCON_MUXMASK;
con &= ~S3C2410_ADCCON_STDBM;
......@@ -153,25 +156,61 @@ int s3c_adc_start(struct s3c_adc_client *client,
}
EXPORT_SYMBOL_GPL(s3c_adc_start);
static void s3c_adc_default_select(unsigned select)
static void s3c_convert_done(struct s3c_adc_client *client,
unsigned v, unsigned u, unsigned *left)
{
client->result = v;
wake_up(client->wait);
}
int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
{
DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
int ret;
client->convert_cb = s3c_convert_done;
client->wait = &wake;
client->result = -1;
ret = s3c_adc_start(client, ch, 1);
if (ret < 0)
goto err;
ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
if (client->result < 0) {
ret = -ETIMEDOUT;
goto err;
}
client->convert_cb = NULL;
return client->result;
err:
return ret;
}
EXPORT_SYMBOL_GPL(s3c_adc_convert);
static void s3c_adc_default_select(struct s3c_adc_client *client,
unsigned select)
{
}
struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned int selected),
void (*conv)(unsigned d0, unsigned d1,
void (*select)(struct s3c_adc_client *client,
unsigned int selected),
void (*conv)(struct s3c_adc_client *client,
unsigned d0, unsigned d1,
unsigned *samples_left),
unsigned int is_ts)
{
struct s3c_adc_client *client;
WARN_ON(!pdev);
WARN_ON(!conv);
if (!select)
select = s3c_adc_default_select;
if (!conv || !pdev)
if (!pdev)
return ERR_PTR(-EINVAL);
client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
......@@ -230,16 +269,19 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
client->nr_samples--;
(client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
if (client->convert_cb)
(client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff,
&client->nr_samples);
if (client->nr_samples > 0) {
/* fire another conversion for this */
client->select_cb(1);
client->select_cb(client, 1);
s3c_adc_convert(adc);
} else {
local_irq_save(flags);
(client->select_cb)(0);
(client->select_cb)(client, 0);
adc->cur = NULL;
s3c_adc_try(adc);
......
arch/arm/plat-s3c24xx/cpu-freq-debugfs.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
*
* Copyright (c) 2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX CPU Frequency scaling - debugfs status support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/err.h>
#include <plat/cpu-freq-core.h>
static struct dentry *dbgfs_root;
static struct dentry *dbgfs_file_io;
static struct dentry *dbgfs_file_info;
static struct dentry *dbgfs_file_board;
#define print_ns(x) ((x) / 10), ((x) % 10)
static void show_max(struct seq_file *seq, struct s3c_freq *f)
{
seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
f->fclk, f->hclk, f->pclk, f->armclk);
}
static int board_show(struct seq_file *seq, void *p)
{
struct s3c_cpufreq_config *cfg;
struct s3c_cpufreq_board *brd;
cfg = s3c_cpufreq_getconfig();
if (!cfg) {
seq_printf(seq, "no configuration registered\n");
return 0;
}
brd = cfg->board;
if (!brd) {
seq_printf(seq, "no board definition set?\n");
return 0;
}
seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
seq_printf(seq, "auto_io=%u\n", brd->auto_io);
seq_printf(seq, "need_io=%u\n", brd->need_io);
show_max(seq, &brd->max);
return 0;
}
static int fops_board_open(struct inode *inode, struct file *file)
{
return single_open(file, board_show, NULL);
}
static const struct file_operations fops_board = {
.open = fops_board_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.owner = THIS_MODULE,
};
static int info_show(struct seq_file *seq, void *p)
{
struct s3c_cpufreq_config *cfg;
cfg = s3c_cpufreq_getconfig();
if (!cfg) {
seq_printf(seq, "no configuration registered\n");
return 0;
}
seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk);
seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n",
cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk);
seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
seq_printf(seq, "\n");
show_max(seq, &cfg->max);
seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
cfg->divs.h_divisor, cfg->divs.p_divisor,
cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
seq_printf(seq, "\n");
seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
return 0;
}
static int fops_info_open(struct inode *inode, struct file *file)
{
return single_open(file, info_show, NULL);
}
static const struct file_operations fops_info = {
.open = fops_info_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.owner = THIS_MODULE,
};
static int io_show(struct seq_file *seq, void *p)
{
void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
struct s3c_cpufreq_config *cfg;
struct s3c_iotimings *iot;
union s3c_iobank *iob;
int bank;
cfg = s3c_cpufreq_getconfig();
if (!cfg) {
seq_printf(seq, "no configuration registered\n");
return 0;
}
show_bank = cfg->info->debug_io_show;
if (!show_bank) {
seq_printf(seq, "no code to show bank timing\n");
return 0;
}
iot = s3c_cpufreq_getiotimings();
if (!iot) {
seq_printf(seq, "no io timings registered\n");
return 0;
}
seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
for (bank = 0; bank < MAX_BANKS; bank++) {
iob = &iot->bank[bank];
seq_printf(seq, "bank %d: ", bank);
if (!iob->io_2410) {
seq_printf(seq, "nothing set\n");
continue;
}
show_bank(seq, cfg, iob);
}
return 0;
}
static int fops_io_open(struct inode *inode, struct file *file)
{
return single_open(file, io_show, NULL);
}
static const struct file_operations fops_io = {
.open = fops_io_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
.owner = THIS_MODULE,
};
static int __init s3c_freq_debugfs_init(void)
{
dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
if (IS_ERR(dbgfs_root)) {
printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
return PTR_ERR(dbgfs_root);
}
dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
NULL, &fops_io);
dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
NULL, &fops_info);
dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
NULL, &fops_board);
return 0;
}
late_initcall(s3c_freq_debugfs_init);
arch/arm/plat-s3c24xx/cpu-freq.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
*
* Copyright (c) 2006,2007,2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX CPU Frequency scaling
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/cpu.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/kobject.h>
#include <linux/sysfs.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/cpu-freq-core.h>
#include <mach/regs-clock.h>
/* note, cpufreq support deals in kHz, no Hz */
static struct cpufreq_driver s3c24xx_driver;
static struct s3c_cpufreq_config cpu_cur;
static struct s3c_iotimings s3c24xx_iotiming;
static struct cpufreq_frequency_table *pll_reg;
static unsigned int last_target = ~0;
static unsigned int ftab_size;
static struct cpufreq_frequency_table *ftab;
static struct clk *_clk_mpll;
static struct clk *_clk_xtal;
static struct clk *clk_fclk;
static struct clk *clk_hclk;
static struct clk *clk_pclk;
static struct clk *clk_arm;
#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
{
return &cpu_cur;
}
struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
{
return &s3c24xx_iotiming;
}
#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
{
unsigned long fclk, pclk, hclk, armclk;
cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
cfg->pll.frequency = fclk;
cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
cfg->divs.h_divisor = fclk / hclk;
cfg->divs.p_divisor = fclk / pclk;
}
static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
{
unsigned long pll = cfg->pll.frequency;
cfg->freq.fclk = pll;
cfg->freq.hclk = pll / cfg->divs.h_divisor;
cfg->freq.pclk = pll / cfg->divs.p_divisor;
/* convert hclk into 10ths of nanoseconds for io calcs */
cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
}
static inline int closer(unsigned int target, unsigned int n, unsigned int c)
{
int diff_cur = abs(target - c);
int diff_new = abs(target - n);
return (diff_new < diff_cur);
}
static void s3c_cpufreq_show(const char *pfx,
struct s3c_cpufreq_config *cfg)
{
s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
cfg->freq.hclk, cfg->divs.h_divisor,
cfg->freq.pclk, cfg->divs.p_divisor);
}
/* functions to wrapper the driver info calls to do the cpu specific work */
static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
{
if (cfg->info->set_iotiming)
(cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
}
static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
{
if (cfg->info->calc_iotiming)
return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
return 0;
}
static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
{
(cfg->info->set_refresh)(cfg);
}
static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
{
(cfg->info->set_divs)(cfg);
}
static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
{
return (cfg->info->calc_divs)(cfg);
}
static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
{
(cfg->info->set_fvco)(cfg);
}
static inline void s3c_cpufreq_resume_clocks(void)
{
cpu_cur.info->resume_clocks();
}
static inline void s3c_cpufreq_updateclk(struct clk *clk,
unsigned int freq)
{
clk_set_rate(clk, freq);
}
static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
unsigned int target_freq,
struct cpufreq_frequency_table *pll)
{
struct s3c_cpufreq_freqs freqs;
struct s3c_cpufreq_config cpu_new;
unsigned long flags;
cpu_new = cpu_cur; /* copy new from current */
s3c_cpufreq_show("cur", &cpu_cur);
/* TODO - check for DMA currently outstanding */
cpu_new.pll = pll ? *pll : cpu_cur.pll;
if (pll)
freqs.pll_changing = 1;
/* update our frequencies */
cpu_new.freq.armclk = target_freq;
cpu_new.freq.fclk = cpu_new.pll.frequency;
if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
printk(KERN_ERR "no divisors for %d\n", target_freq);
goto err_notpossible;
}
s3c_freq_dbg("%s: got divs\n", __func__);
s3c_cpufreq_calc(&cpu_new);
s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
if (s3c_cpufreq_calcio(&cpu_new) < 0) {
printk(KERN_ERR "%s: no IO timings\n", __func__);
goto err_notpossible;
}
}
s3c_cpufreq_show("new", &cpu_new);
/* setup our cpufreq parameters */
freqs.old = cpu_cur.freq;
freqs.new = cpu_new.freq;
freqs.freqs.cpu = 0;
freqs.freqs.old = cpu_cur.freq.armclk / 1000;
freqs.freqs.new = cpu_new.freq.armclk / 1000;
/* update f/h/p clock settings before we issue the change
* notification, so that drivers do not need to do anything
* special if they want to recalculate on CPUFREQ_PRECHANGE. */
s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
/* start the frequency change */
if (policy)
cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
/* If hclk is staying the same, then we do not need to
* re-write the IO or the refresh timings whilst we are changing
* speed. */
local_irq_save(flags);
/* is our memory clock slowing down? */
if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
s3c_cpufreq_setrefresh(&cpu_new);
s3c_cpufreq_setio(&cpu_new);
}
if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
/* not changing PLL, just set the divisors */
s3c_cpufreq_setdivs(&cpu_new);
} else {
if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
/* slow the cpu down, then set divisors */
s3c_cpufreq_setfvco(&cpu_new);
s3c_cpufreq_setdivs(&cpu_new);
} else {
/* set the divisors, then speed up */
s3c_cpufreq_setdivs(&cpu_new);
s3c_cpufreq_setfvco(&cpu_new);
}
}
/* did our memory clock speed up */
if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
s3c_cpufreq_setrefresh(&cpu_new);
s3c_cpufreq_setio(&cpu_new);
}
/* update our current settings */
cpu_cur = cpu_new;
local_irq_restore(flags);
/* notify everyone we've done this */
if (policy)
cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
s3c_freq_dbg("%s: finished\n", __func__);
return 0;
err_notpossible:
printk(KERN_ERR "no compatible settings for %d\n", target_freq);
return -EINVAL;
}
/* s3c_cpufreq_target
*
* called by the cpufreq core to adjust the frequency that the CPU
* is currently running at.
*/
static int s3c_cpufreq_target(struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
struct cpufreq_frequency_table *pll;
unsigned int index;
/* avoid repeated calls which cause a needless amout of duplicated
* logging output (and CPU time as the calculation process is
* done) */
if (target_freq == last_target)
return 0;
last_target = target_freq;
s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
__func__, policy, target_freq, relation);
if (ftab) {
if (cpufreq_frequency_table_target(policy, ftab,
target_freq, relation,
&index)) {
s3c_freq_dbg("%s: table failed\n", __func__);
return -EINVAL;
}
s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
target_freq, index, ftab[index].frequency);
target_freq = ftab[index].frequency;
}
target_freq *= 1000; /* convert target to Hz */
/* find the settings for our new frequency */
if (!pll_reg || cpu_cur.lock_pll) {
/* either we've not got any PLL values, or we've locked
* to the current one. */
pll = NULL;
} else {
struct cpufreq_policy tmp_policy;
int ret;
/* we keep the cpu pll table in Hz, to ensure we get an
* accurate value for the PLL output. */
tmp_policy.min = policy->min * 1000;
tmp_policy.max = policy->max * 1000;
tmp_policy.cpu = policy->cpu;
/* cpufreq_frequency_table_target uses a pointer to 'index'
* which is the number of the table entry, not the value of
* the table entry's index field. */
ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
target_freq, relation,
&index);
if (ret < 0) {
printk(KERN_ERR "%s: no PLL available\n", __func__);
goto err_notpossible;
}
pll = pll_reg + index;
s3c_freq_dbg("%s: target %u => %u\n",
__func__, target_freq, pll->frequency);
target_freq = pll->frequency;
}
return s3c_cpufreq_settarget(policy, target_freq, pll);
err_notpossible:
printk(KERN_ERR "no compatible settings for %d\n", target_freq);
return -EINVAL;
}
static unsigned int s3c_cpufreq_get(unsigned int cpu)
{
return clk_get_rate(clk_arm) / 1000;
}
struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
{
struct clk *clk;
clk = clk_get(dev, name);
if (IS_ERR(clk))
printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
return clk;
}
static int s3c_cpufreq_init(struct cpufreq_policy *policy)
{
printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
if (policy->cpu != 0)
return -EINVAL;
policy->cur = s3c_cpufreq_get(0);
policy->min = policy->cpuinfo.min_freq = 0;
policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
/* feed the latency information from the cpu driver */
policy->cpuinfo.transition_latency = cpu_cur.info->latency;
if (ftab)
cpufreq_frequency_table_cpuinfo(policy, ftab);
return 0;
}
static __init int s3c_cpufreq_initclks(void)
{
_clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
_clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
return -ENOENT;
}
printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
clk_get_rate(clk_fclk) / 1000,
clk_get_rate(clk_hclk) / 1000,
clk_get_rate(clk_pclk) / 1000,
clk_get_rate(clk_arm) / 1000);
return 0;
}
static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
{
if (policy->cpu != 0)
return -EINVAL;
return 0;
}
#ifdef CONFIG_PM
static struct cpufreq_frequency_table suspend_pll;
static unsigned int suspend_freq;
static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
{
suspend_pll.frequency = clk_get_rate(_clk_mpll);
suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
suspend_freq = s3c_cpufreq_get(0) * 1000;
return 0;
}
static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
{
int ret;
s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
last_target = ~0; /* invalidate last_target setting */
/* first, find out what speed we resumed at. */
s3c_cpufreq_resume_clocks();
/* whilst we will be called later on, we try and re-set the
* cpu frequencies as soon as possible so that we do not end
* up resuming devices and then immediatley having to re-set
* a number of settings once these devices have restarted.
*
* as a note, it is expected devices are not used until they
* have been un-suspended and at that time they should have
* used the updated clock settings.
*/
ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
if (ret) {
printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
return ret;
}
return 0;
}
#else
#define s3c_cpufreq_resume NULL
#define s3c_cpufreq_suspend NULL
#endif
static struct cpufreq_driver s3c24xx_driver = {
.flags = CPUFREQ_STICKY,
.verify = s3c_cpufreq_verify,
.target = s3c_cpufreq_target,
.get = s3c_cpufreq_get,
.init = s3c_cpufreq_init,
.suspend = s3c_cpufreq_suspend,
.resume = s3c_cpufreq_resume,
.name = "s3c24xx",
};
int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
{
if (!info || !info->name) {
printk(KERN_ERR "%s: failed to pass valid information\n",
__func__);
return -EINVAL;
}
printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
info->name);
/* check our driver info has valid data */
BUG_ON(info->set_refresh == NULL);
BUG_ON(info->set_divs == NULL);
BUG_ON(info->calc_divs == NULL);
/* info->set_fvco is optional, depending on whether there
* is a need to set the clock code. */
cpu_cur.info = info;
/* Note, driver registering should probably update locktime */
return 0;
}
int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
{
struct s3c_cpufreq_board *ours;
if (!board) {
printk(KERN_INFO "%s: no board data\n", __func__);
return -EINVAL;
}
/* Copy the board information so that each board can make this
* initdata. */
ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
if (ours == NULL) {
printk(KERN_ERR "%s: no memory\n", __func__);
return -ENOMEM;
}
*ours = *board;
cpu_cur.board = ours;
return 0;
}
int __init s3c_cpufreq_auto_io(void)
{
int ret;
if (!cpu_cur.info->get_iotiming) {
printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
return -ENOENT;
}
printk(KERN_INFO "%s: working out IO settings\n", __func__);
ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
if (ret)
printk(KERN_ERR "%s: failed to get timings\n", __func__);
return ret;
}
/* if one or is zero, then return the other, otherwise return the min */
#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
/**
* s3c_cpufreq_freq_min - find the minimum settings for the given freq.
* @dst: The destination structure
* @a: One argument.
* @b: The other argument.
*
* Create a minimum of each frequency entry in the 'struct s3c_freq',
* unless the entry is zero when it is ignored and the non-zero argument
* used.
*/
static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
struct s3c_freq *a, struct s3c_freq *b)
{
dst->fclk = do_min(a->fclk, b->fclk);
dst->hclk = do_min(a->hclk, b->hclk);
dst->pclk = do_min(a->pclk, b->pclk);
dst->armclk = do_min(a->armclk, b->armclk);
}
static inline u32 calc_locktime(u32 freq, u32 time_us)
{
u32 result;
result = freq * time_us;
result = DIV_ROUND_UP(result, 1000 * 1000);
return result;
}
static void s3c_cpufreq_update_loctkime(void)
{
unsigned int bits = cpu_cur.info->locktime_bits;
u32 rate = (u32)clk_get_rate(_clk_xtal);
u32 val;
if (bits == 0) {
WARN_ON(1);
return;
}
val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
val |= calc_locktime(rate, cpu_cur.info->locktime_m);
printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
__raw_writel(val, S3C2410_LOCKTIME);
}
static int s3c_cpufreq_build_freq(void)
{
int size, ret;
if (!cpu_cur.info->calc_freqtable)
return -EINVAL;
kfree(ftab);
ftab = NULL;
size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
size++;
ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
if (!ftab) {
printk(KERN_ERR "%s: no memory for tables\n", __func__);
return -ENOMEM;
}
ftab_size = size;
ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
return 0;
}
static int __init s3c_cpufreq_initcall(void)
{
int ret = 0;
if (cpu_cur.info && cpu_cur.board) {
ret = s3c_cpufreq_initclks();
if (ret)
goto out;
/* get current settings */
s3c_cpufreq_getcur(&cpu_cur);
s3c_cpufreq_show("cur", &cpu_cur);
if (cpu_cur.board->auto_io) {
ret = s3c_cpufreq_auto_io();
if (ret) {
printk(KERN_ERR "%s: failed to get io timing\n",
__func__);
goto out;
}
}
if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
printk(KERN_ERR "%s: no IO support registered\n",
__func__);
ret = -EINVAL;
goto out;
}
if (!cpu_cur.info->need_pll)
cpu_cur.lock_pll = 1;
s3c_cpufreq_update_loctkime();
s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
&cpu_cur.info->max);
if (cpu_cur.info->calc_freqtable)
s3c_cpufreq_build_freq();
ret = cpufreq_register_driver(&s3c24xx_driver);
}
out:
return ret;
}
late_initcall(s3c_cpufreq_initcall);
/**
* s3c_plltab_register - register CPU PLL table.
* @plls: The list of PLL entries.
* @plls_no: The size of the PLL entries @plls.
*
* Register the given set of PLLs with the system.
*/
int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
unsigned int plls_no)
{
struct cpufreq_frequency_table *vals;
unsigned int size;
size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
vals = kmalloc(size, GFP_KERNEL);
if (vals) {
memcpy(vals, plls, size);
pll_reg = vals;
/* write a terminating entry, we don't store it in the
* table that is stored in the kernel */
vals += plls_no;
vals->frequency = CPUFREQ_TABLE_END;
printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
} else
printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
return vals ? 0 : -ENOMEM;
}
arch/arm/plat-s3c24xx/cpu.c
View file @ 29c08460
......@@ -81,7 +81,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.map_io = s3c2410_map_io,
.init_clocks = s3c2410_init_clocks,
.init_uarts = s3c2410_init_uarts,
.init = s3c2410_init,
.init = s3c2410a_init,
.name = name_s3c2410a
},
{
......
arch/arm/plat-s3c24xx/devs.c
View file @ 29c08460
......@@ -26,6 +26,8 @@
#include <asm/mach/irq.h>
#include <mach/fb.h>
#include <mach/hardware.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <asm/irq.h>
#include <plat/regs-serial.h>
......@@ -180,25 +182,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
}
}
/* NAND Controller */
static struct resource s3c_nand_resource[] = {
[0] = {
.start = S3C24XX_PA_NAND,
.end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
.flags = IORESOURCE_MEM,
}
};
struct platform_device s3c_device_nand = {
.name = "s3c2410-nand",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_nand_resource),
.resource = s3c_nand_resource,
};
EXPORT_SYMBOL(s3c_device_nand);
/* USB Device (Gadget)*/
static struct resource s3c_usbgadget_resource[] = {
......@@ -348,7 +331,7 @@ struct platform_device s3c_device_adc = {
/* HWMON */
struct platform_device s3c_device_hwmon = {
.name = "s3c24xx-hwmon",
.name = "s3c-hwmon",
.id = -1,
.dev.parent = &s3c_device_adc.dev,
};
......@@ -473,4 +456,52 @@ struct platform_device s3c_device_camif = {
EXPORT_SYMBOL(s3c_device_camif);
/* AC97 */
static struct resource s3c_ac97_resource[] = {
[0] = {
.start = S3C2440_PA_AC97,
.end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3C244x_AC97,
.end = IRQ_S3C244x_AC97,
.flags = IORESOURCE_IRQ,
},
[2] = {
.name = "PCM out",
.start = DMACH_PCM_OUT,
.end = DMACH_PCM_OUT,
.flags = IORESOURCE_DMA,
},
[3] = {
.name = "PCM in",
.start = DMACH_PCM_IN,
.end = DMACH_PCM_IN,
.flags = IORESOURCE_DMA,
},
[4] = {
.name = "Mic in",
.start = DMACH_MIC_IN,
.end = DMACH_MIC_IN,
.flags = IORESOURCE_DMA,
},
};
static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
struct platform_device s3c_device_ac97 = {
.name = "s3c-ac97",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_ac97_resource),
.resource = s3c_ac97_resource,
.dev = {
.dma_mask = &s3c_device_ac97_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
EXPORT_SYMBOL(s3c_device_ac97);
#endif // CONFIG_CPU_S32440
arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h 0 → 100644
View file @ 29c08460
/* arch/arm/plat-s3c/include/plat/cpu-freq.h
*
* Copyright (c) 2006,2007,2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C CPU frequency scaling support - core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/cpu-freq.h>
struct seq_file;
#define MAX_BANKS (8)
#define S3C2412_MAX_IO (8)
/**
* struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
* @bankcon: The cached version of settings in this structure.
* @tacp:
* @tacs: Time from address valid to nCS asserted.
* @tcos: Time from nCS asserted to nOE or nWE asserted.
* @tacc: Time that nOE or nWE is asserted.
* @tcoh: Time nCS is held after nOE or nWE are released.
* @tcah: Time address is held for after
* @nwait_en: Whether nWAIT is enabled for this bank.
*
* This structure represents the IO timings for a S3C2410 style IO bank
* used by the CPU frequency support if it needs to change the settings
* of the IO.
*/
struct s3c2410_iobank_timing {
unsigned long bankcon;
unsigned int tacp;
unsigned int tacs;
unsigned int tcos;
unsigned int tacc;
unsigned int tcoh; /* nCS hold afrer nOE/nWE */
unsigned int tcah; /* Address hold after nCS */
unsigned char nwait_en; /* nWait enabled for bank. */
};
/**
* struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
* @idcy: The idle cycle time between transactions.
* @wstrd: nCS release to end of read cycle.
* @wstwr: nCS release to end of write cycle.
* @wstoen: nCS assertion to nOE assertion time.
* @wstwen: nCS assertion to nWE assertion time.
* @wstbrd: Burst ready delay.
* @smbidcyr: Register cache for smbidcyr value.
* @smbwstrd: Register cache for smbwstrd value.
* @smbwstwr: Register cache for smbwstwr value.
* @smbwstoen: Register cache for smbwstoen value.
* @smbwstwen: Register cache for smbwstwen value.
* @smbwstbrd: Register cache for smbwstbrd value.
*
* Timing information for a IO bank on an S3C2412 or similar system which
* uses a PL093 block.
*/
struct s3c2412_iobank_timing {
unsigned int idcy;
unsigned int wstrd;
unsigned int wstwr;
unsigned int wstoen;
unsigned int wstwen;
unsigned int wstbrd;
/* register cache */
unsigned char smbidcyr;
unsigned char smbwstrd;
unsigned char smbwstwr;
unsigned char smbwstoen;
unsigned char smbwstwen;
unsigned char smbwstbrd;
};
union s3c_iobank {
struct s3c2410_iobank_timing *io_2410;
struct s3c2412_iobank_timing *io_2412;
};
/**
* struct s3c_iotimings - Chip IO timings holder
* @bank: The timings for each IO bank.
*/
struct s3c_iotimings {
union s3c_iobank bank[MAX_BANKS];
};
/**
* struct s3c_plltab - PLL table information.
* @vals: List of PLL values.
* @size: Size of the PLL table @vals.
*/
struct s3c_plltab {
struct s3c_pllval *vals;
int size;
};
/**
* struct s3c_cpufreq_config - current cpu frequency configuration
* @freq: The current settings for the core clocks.
* @max: Maxium settings, derived from core, board and user settings.
* @pll: The PLL table entry for the current PLL settings.
* @divs: The divisor settings for the core clocks.
* @info: The current core driver information.
* @board: The information for the board we are running on.
* @lock_pll: Set if the PLL settings cannot be changed.
*
* This is for the core drivers that need to know information about
* the current settings and values. It should not be needed by any
* device drivers.
*/
struct s3c_cpufreq_config {
struct s3c_freq freq;
struct s3c_freq max;
struct cpufreq_frequency_table pll;
struct s3c_clkdivs divs;
struct s3c_cpufreq_info *info; /* for core, not drivers */
struct s3c_cpufreq_board *board;
unsigned int lock_pll:1;
};
/**
* struct s3c_cpufreq_info - Information for the CPU frequency driver.
* @name: The name of this implementation.
* @max: The maximum frequencies for the system.
* @latency: Transition latency to give to cpufreq.
* @locktime_m: The lock-time in uS for the MPLL.
* @locktime_u: The lock-time in uS for the UPLL.
* @locttime_bits: The number of bits each LOCKTIME field.
* @need_pll: Set if this driver needs to change the PLL values to acheive
* any frequency changes. This is really only need by devices like the
* S3C2410 where there is no or limited divider between the PLL and the
* ARMCLK.
* @resume_clocks: Update the clocks on resume.
* @get_iotiming: Get the current IO timing data, mainly for use at start.
* @set_iotiming: Update the IO timings from the cached copies calculated
* from the @calc_iotiming entry when changing the frequency.
* @calc_iotiming: Calculate and update the cached copies of the IO timings
* from the newly calculated frequencies.
* @calc_freqtable: Calculate (fill in) the given frequency table from the
* current frequency configuration. If the table passed in is NULL,
* then the return is the number of elements to be filled for allocation
* of the table.
* @set_refresh: Set the memory refresh configuration.
* @set_fvco: Set the PLL frequencies.
* @set_divs: Update the clock divisors.
* @calc_divs: Calculate the clock divisors.
*/
struct s3c_cpufreq_info {
const char *name;
struct s3c_freq max;
unsigned int latency;
unsigned int locktime_m;
unsigned int locktime_u;
unsigned char locktime_bits;
unsigned int need_pll:1;
/* driver routines */
void (*resume_clocks)(void);
int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings);
void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings);
int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings);
int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
struct cpufreq_frequency_table *t,
size_t table_size);
void (*debug_io_show)(struct seq_file *seq,
struct s3c_cpufreq_config *cfg,
union s3c_iobank *iob);
void (*set_refresh)(struct s3c_cpufreq_config *cfg);
void (*set_fvco)(struct s3c_cpufreq_config *cfg);
void (*set_divs)(struct s3c_cpufreq_config *cfg);
int (*calc_divs)(struct s3c_cpufreq_config *cfg);
};
extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no);
/* exports and utilities for debugfs */
extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
struct s3c_cpufreq_config *cfg,
union s3c_iobank *iob);
extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
struct s3c_cpufreq_config *cfg,
union s3c_iobank *iob);
#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
#define s3c_cpufreq_debugfs_call(x) x
#else
#define s3c_cpufreq_debugfs_call(x) NULL
#endif
/* Useful utility functions. */
extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
/* S3C2410 and compatible exported functions */
extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot);
extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings);
extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot);
extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
/* S3C2412 compatible routines */
extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings);
extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings);
extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot);
extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot);
#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
#define s3c_freq_dbg(x...) printk(KERN_INFO x)
#else
#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
#else
#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
int index, size_t table_size,
unsigned int freq)
{
if (index < 0)
return index;
if (table) {
if (index >= table_size)
return -ENOMEM;
s3c_freq_dbg("%s: { %d = %u kHz }\n",
__func__, index, freq);
table[index].index = index;
table[index].frequency = freq;
}
return index + 1;
}
arch/arm/plat-s3c24xx/include/plat/fiq.h 0 → 100644
View file @ 29c08460
/* linux/include/asm-arm/plat-s3c24xx/fiq.h
*
* Copyright (c) 2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Header file for S3C24XX CPU FIQ support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
extern int s3c24xx_set_fiq(unsigned int irq, bool on);
arch/arm/plat-s3c24xx/include/plat/s3c2410.h
View file @ 29c08460
......@@ -14,6 +14,7 @@
#ifdef CONFIG_CPU_S3C2410
extern int s3c2410_init(void);
extern int s3c2410a_init(void);
extern void s3c2410_map_io(void);
......
arch/arm/plat-s3c24xx/irq.c
View file @ 29c08460
......@@ -493,6 +493,38 @@ s3c_irq_demux_extint4t7(unsigned int irq,
}
}
#ifdef CONFIG_FIQ
/**
* s3c24xx_set_fiq - set the FIQ routing
* @irq: IRQ number to route to FIQ on processor.
* @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
*
* Change the state of the IRQ to FIQ routing depending on @irq and @on. If
* @on is true, the @irq is checked to see if it can be routed and the
* interrupt controller updated to route the IRQ. If @on is false, the FIQ
* routing is cleared, regardless of which @irq is specified.
*/
int s3c24xx_set_fiq(unsigned int irq, bool on)
{
u32 intmod;
unsigned offs;
if (on) {
offs = irq - FIQ_START;
if (offs > 31)
return -EINVAL;
intmod = 1 << offs;
} else {
intmod = 0;
}
__raw_writel(intmod, S3C2410_INTMOD);
return 0;
}
#endif
/* s3c24xx_init_irq
*
* Initialise S3C2410 IRQ system
......@@ -505,6 +537,10 @@ void __init s3c24xx_init_irq(void)
int irqno;
int i;
#ifdef CONFIG_FIQ
init_FIQ();
#endif
irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
/* first, clear all interrupts pending... */
......
arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
*
* Copyright (c) 2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/io.h>
#include <mach/map.h>
#include <mach/regs-mem.h>
#include <mach/regs-clock.h>
#include <plat/cpu-freq-core.h>
/**
* s3c2410_cpufreq_setrefresh - set SDRAM refresh value
* @cfg: The frequency configuration
*
* Set the SDRAM refresh value appropriately for the configured
* frequency.
*/
void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
{
struct s3c_cpufreq_board *board = cfg->board;
unsigned long refresh;
unsigned long refval;
/* Reduce both the refresh time (in ns) and the frequency (in MHz)
* down to ensure that we do not overflow 32 bit numbers.
*
* This should work for HCLK up to 133MHz and refresh period up
* to 30usec.
*/
refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
refresh = (1 << 11) + 1 - refresh;
s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
refval = __raw_readl(S3C2410_REFRESH);
refval &= ~((1 << 12) - 1);
refval |= refresh;
__raw_writel(refval, S3C2410_REFRESH);
}
/**
* s3c2410_set_fvco - set the PLL value
* @cfg: The frequency configuration
*/
void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
{
__raw_writel(cfg->pll.index, S3C2410_MPLLCON);
}
arch/arm/plat-s3c24xx/s3c2410-iotiming.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
*
* Copyright (c) 2006,2008,2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/seq_file.h>
#include <linux/io.h>
#include <mach/map.h>
#include <mach/regs-mem.h>
#include <mach/regs-clock.h>
#include <plat/cpu-freq-core.h>
#define print_ns(x) ((x) / 10), ((x) % 10)
/**
* s3c2410_print_timing - print bank timing data for debug purposes
* @pfx: The prefix to put on the output
* @timings: The timing inforamtion to print.
*/
static void s3c2410_print_timing(const char *pfx,
struct s3c_iotimings *timings)
{
struct s3c2410_iobank_timing *bt;
int bank;
for (bank = 0; bank < MAX_BANKS; bank++) {
bt = timings->bank[bank].io_2410;
if (!bt)
continue;
printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
"Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
print_ns(bt->tacs),
print_ns(bt->tcos),
print_ns(bt->tacc),
print_ns(bt->tcoh),
print_ns(bt->tcah));
}
}
/**
* bank_reg - convert bank number to pointer to the control register.
* @bank: The IO bank number.
*/
static inline void __iomem *bank_reg(unsigned int bank)
{
return S3C2410_BANKCON0 + (bank << 2);
}
/**
* bank_is_io - test whether bank is used for IO
* @bankcon: The bank control register.
*
* This is a simplistic test to see if any BANKCON[x] is not an IO
* bank. It currently does not take into account whether BWSCON has
* an illegal width-setting in it, or if the pin connected to nCS[x]
* is actually being handled as a chip-select.
*/
static inline int bank_is_io(unsigned long bankcon)
{
return !(bankcon & S3C2410_BANKCON_SDRAM);
}
/**
* to_div - convert cycle time to divisor
* @cyc: The cycle time, in 10ths of nanoseconds.
* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
*
* Convert the given cycle time into the divisor to use to obtain it from
* HCLK.
*/
static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
{
if (cyc == 0)
return 0;
return DIV_ROUND_UP(cyc, hclk_tns);
}
/**
* calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
* @cyc: The cycle time, in 10ths of nanoseconds.
* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
* @v: Pointer to register to alter.
* @shift: The shift to get to the control bits.
*
* Calculate the divisor, and turn it into the correct control bits to
* set in the result, @v.
*/
static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
unsigned long *v, int shift)
{
unsigned int div = to_div(cyc, hclk_tns);
unsigned long val;
s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
__func__, cyc, hclk_tns, shift, div);
switch (div) {
case 0:
val = 0;
break;
case 1:
val = 1;
break;
case 2:
val = 2;
break;
case 3:
case 4:
val = 3;
break;
default:
return -1;
}
*v |= val << shift;
return 0;
}
int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
{
/* Currently no support for Tacp calculations. */
return 0;
}
/**
* calc_tacc - calculate divisor control for tacc.
* @cyc: The cycle time, in 10ths of nanoseconds.
* @nwait_en: IS nWAIT enabled for this bank.
* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
* @v: Pointer to register to alter.
*
* Calculate the divisor control for tACC, taking into account whether
* the bank has nWAIT enabled. The result is used to modify the value
* pointed to by @v.
*/
static int calc_tacc(unsigned int cyc, int nwait_en,
unsigned long hclk_tns, unsigned long *v)
{
unsigned int div = to_div(cyc, hclk_tns);
unsigned long val;
s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
__func__, cyc, nwait_en, hclk_tns, div);
/* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
if (nwait_en && div < 4)
div = 4;
switch (div) {
case 0:
val = 0;
break;
case 1:
case 2:
case 3:
case 4:
val = div - 1;
break;
case 5:
case 6:
val = 4;
break;
case 7:
case 8:
val = 5;
break;
case 9:
case 10:
val = 6;
break;
case 11:
case 12:
case 13:
case 14:
val = 7;
break;
default:
return -1;
}
*v |= val << 8;
return 0;
}
/**
* s3c2410_calc_bank - calculate bank timing infromation
* @cfg: The configuration we need to calculate for.
* @bt: The bank timing information.
*
* Given the cycle timine for a bank @bt, calculate the new BANKCON
* setting for the @cfg timing. This updates the timing information
* ready for the cpu frequency change.
*/
static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
struct s3c2410_iobank_timing *bt)
{
unsigned long hclk = cfg->freq.hclk_tns;
unsigned long res;
int ret;
res = bt->bankcon;
res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
/* tacp: 2,3,4,5 */
/* tcah: 0,1,2,4 */
/* tcoh: 0,1,2,4 */
/* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
/* tcos: 0,1,2,4 */
/* tacs: 0,1,2,4 */
ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
if (ret)
return -EINVAL;
ret |= calc_tacp(bt->tacp, hclk, &res);
ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
if (ret)
return -EINVAL;
bt->bankcon = res;
return 0;
}
static unsigned int tacc_tab[] = {
[0] = 1,
[1] = 2,
[2] = 3,
[3] = 4,
[4] = 6,
[5] = 9,
[6] = 10,
[7] = 14,
};
/**
* get_tacc - turn tACC value into cycle time
* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
* @val: The bank timing register value, shifed down.
*/
static unsigned int get_tacc(unsigned long hclk_tns,
unsigned long val)
{
val &= 7;
return hclk_tns * tacc_tab[val];
}
/**
* get_0124 - turn 0/1/2/4 divider into cycle time
* @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
* @val: The bank timing register value, shifed down.
*/
static unsigned int get_0124(unsigned long hclk_tns,
unsigned long val)
{
val &= 3;
return hclk_tns * ((val == 3) ? 4 : val);
}
/**
* s3c2410_iotiming_getbank - turn BANKCON into cycle time information
* @cfg: The frequency configuration
* @bt: The bank timing to fill in (uses cached BANKCON)
*
* Given the BANKCON setting in @bt and the current frequency settings
* in @cfg, update the cycle timing information.
*/
void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
struct s3c2410_iobank_timing *bt)
{
unsigned long bankcon = bt->bankcon;
unsigned long hclk = cfg->freq.hclk_tns;
bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
}
/**
* s3c2410_iotiming_debugfs - debugfs show io bank timing information
* @seq: The seq_file to write output to using seq_printf().
* @cfg: The current configuration.
* @iob: The IO bank information to decode.
*/
void s3c2410_iotiming_debugfs(struct seq_file *seq,
struct s3c_cpufreq_config *cfg,
union s3c_iobank *iob)
{
struct s3c2410_iobank_timing *bt = iob->io_2410;
unsigned long bankcon = bt->bankcon;
unsigned long hclk = cfg->freq.hclk_tns;
unsigned int tacs;
unsigned int tcos;
unsigned int tacc;
unsigned int tcoh;
unsigned int tcah;
seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
seq_printf(seq,
"\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
print_ns(bt->tacs),
print_ns(bt->tcos),
print_ns(bt->tacc),
print_ns(bt->tcoh),
print_ns(bt->tcah));
seq_printf(seq,
"\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
print_ns(tacs),
print_ns(tcos),
print_ns(tacc),
print_ns(tcoh),
print_ns(tcah));
}
/**
* s3c2410_iotiming_calc - Calculate bank timing for frequency change.
* @cfg: The frequency configuration
* @iot: The IO timing information to fill out.
*
* Calculate the new values for the banks in @iot based on the new
* frequency information in @cfg. This is then used by s3c2410_iotiming_set()
* to update the timing when necessary.
*/
int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot)
{
struct s3c2410_iobank_timing *bt;
unsigned long bankcon;
int bank;
int ret;
for (bank = 0; bank < MAX_BANKS; bank++) {
bankcon = __raw_readl(bank_reg(bank));
bt = iot->bank[bank].io_2410;
if (!bt)
continue;
bt->bankcon = bankcon;
ret = s3c2410_calc_bank(cfg, bt);
if (ret) {
printk(KERN_ERR "%s: cannot calculate bank %d io\n",
__func__, bank);
goto err;
}
s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
__func__, bank, bt->bankcon);
}
return 0;
err:
return ret;
}
/**
* s3c2410_iotiming_set - set the IO timings from the given setup.
* @cfg: The frequency configuration
* @iot: The IO timing information to use.
*
* Set all the currently used IO bank timing information generated
* by s3c2410_iotiming_calc() once the core has validated that all
* the new values are within permitted bounds.
*/
void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot)
{
struct s3c2410_iobank_timing *bt;
int bank;
/* set the io timings from the specifier */
for (bank = 0; bank < MAX_BANKS; bank++) {
bt = iot->bank[bank].io_2410;
if (!bt)
continue;
__raw_writel(bt->bankcon, bank_reg(bank));
}
}
/**
* s3c2410_iotiming_get - Get the timing information from current registers.
* @cfg: The frequency configuration
* @timings: The IO timing information to fill out.
*
* Calculate the @timings timing information from the current frequency
* information in @cfg, and the new frequency configur
* through all the IO banks, reading the state and then updating @iot
* as necessary.
*
* This is used at the moment on initialisation to get the current
* configuration so that boards do not have to carry their own setup
* if the timings are correct on initialisation.
*/
int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings)
{
struct s3c2410_iobank_timing *bt;
unsigned long bankcon;
unsigned long bwscon;
int bank;
bwscon = __raw_readl(S3C2410_BWSCON);
/* look through all banks to see what is currently set. */
for (bank = 0; bank < MAX_BANKS; bank++) {
bankcon = __raw_readl(bank_reg(bank));
if (!bank_is_io(bankcon))
continue;
s3c_freq_iodbg("%s: bank %d: con %08lx\n",
__func__, bank, bankcon);
bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
if (!bt) {
printk(KERN_ERR "%s: no memory for bank\n", __func__);
return -ENOMEM;
}
/* find out in nWait is enabled for bank. */
if (bank != 0) {
unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank);
if (tmp & S3C2410_BWSCON_WS)
bt->nwait_en = 1;
}
timings->bank[bank].io_2410 = bt;
bt->bankcon = bankcon;
s3c2410_iotiming_getbank(cfg, bt);
}
s3c2410_print_timing("get", timings);
return 0;
}
arch/arm/plat-s3c24xx/s3c2412-iotiming.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
*
* Copyright (c) 2006,2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2412/S3C2443 (PL093 based) IO timing support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/seq_file.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/amba/pl093.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/regs-s3c2412-mem.h>
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
#include <plat/clock.h>
#define print_ns(x) ((x) / 10), ((x) % 10)
/**
* s3c2412_print_timing - print timing infromation via printk.
* @pfx: The prefix to print each line with.
* @iot: The IO timing information
*/
static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
{
struct s3c2412_iobank_timing *bt;
unsigned int bank;
for (bank = 0; bank < MAX_BANKS; bank++) {
bt = iot->bank[bank].io_2412;
if (!bt)
continue;
printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
"wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
print_ns(bt->idcy),
print_ns(bt->wstrd),
print_ns(bt->wstwr),
print_ns(bt->wstoen),
print_ns(bt->wstwen),
print_ns(bt->wstbrd));
}
}
/**
* to_div - turn a cycle length into a divisor setting.
* @cyc_tns: The cycle time in 10ths of nanoseconds.
* @clk_tns: The clock period in 10ths of nanoseconds.
*/
static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
{
return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
}
/**
* calc_timing - calculate timing divisor value and check in range.
* @hwtm: The hardware timing in 10ths of nanoseconds.
* @clk_tns: The clock period in 10ths of nanoseconds.
* @err: Pointer to err variable to update in event of failure.
*/
static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
unsigned int *err)
{
unsigned int ret = to_div(hwtm, clk_tns);
if (ret > 0xf)
*err = -EINVAL;
return ret;
}
/**
* s3c2412_calc_bank - calculate the bank divisor settings.
* @cfg: The current frequency configuration.
* @bt: The bank timing.
*/
static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
struct s3c2412_iobank_timing *bt)
{
unsigned int hclk = cfg->freq.hclk_tns;
int err = 0;
bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
return err;
}
/**
* s3c2412_iotiming_debugfs - debugfs show io bank timing information
* @seq: The seq_file to write output to using seq_printf().
* @cfg: The current configuration.
* @iob: The IO bank information to decode.
*/
void s3c2412_iotiming_debugfs(struct seq_file *seq,
struct s3c_cpufreq_config *cfg,
union s3c_iobank *iob)
{
struct s3c2412_iobank_timing *bt = iob->io_2412;
seq_printf(seq,
"\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
"wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
print_ns(bt->idcy),
print_ns(bt->wstrd),
print_ns(bt->wstwr),
print_ns(bt->wstoen),
print_ns(bt->wstwen),
print_ns(bt->wstbrd));
}
/**
* s3c2412_iotiming_calc - calculate all the bank divisor settings.
* @cfg: The current frequency configuration.
* @iot: The bank timing information.
*
* Calculate the timing information for all the banks that are
* configured as IO, using s3c2412_calc_bank().
*/
int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot)
{
struct s3c2412_iobank_timing *bt;
int bank;
int ret;
for (bank = 0; bank < MAX_BANKS; bank++) {
bt = iot->bank[bank].io_2412;
if (!bt)
continue;
ret = s3c2412_calc_bank(cfg, bt);
if (ret) {
printk(KERN_ERR "%s: cannot calculate bank %d io\n",
__func__, bank);
goto err;
}
}
return 0;
err:
return ret;
}
/**
* s3c2412_iotiming_set - set the timing information
* @cfg: The current frequency configuration.
* @iot: The bank timing information.
*
* Set the IO bank information from the details calculated earlier from
* calling s3c2412_iotiming_calc().
*/
void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *iot)
{
struct s3c2412_iobank_timing *bt;
void __iomem *regs;
int bank;
/* set the io timings from the specifier */
for (bank = 0; bank < MAX_BANKS; bank++) {
bt = iot->bank[bank].io_2412;
if (!bt)
continue;
regs = S3C2412_SSMC_BANK(bank);
__raw_writel(bt->smbidcyr, regs + SMBIDCYR);
__raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
__raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
__raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
__raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
__raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
}
}
static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
{
return (reg & 0xf) * clock;
}
static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
struct s3c2412_iobank_timing *bt,
unsigned int bank)
{
unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */
void __iomem *regs = S3C2412_SSMC_BANK(bank);
bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
}
/**
* bank_is_io - return true if bank is (possibly) IO.
* @bank: The bank number.
* @bankcfg: The value of S3C2412_EBI_BANKCFG.
*/
static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
{
if (bank < 2)
return true;
return !(bankcfg & (1 << bank));
}
int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
struct s3c_iotimings *timings)
{
struct s3c2412_iobank_timing *bt;
u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
unsigned int bank;
/* look through all banks to see what is currently set. */
for (bank = 0; bank < MAX_BANKS; bank++) {
if (!bank_is_io(bank, bankcfg))
continue;
bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL);
if (!bt) {
printk(KERN_ERR "%s: no memory for bank\n", __func__);
return -ENOMEM;
}
timings->bank[bank].io_2412 = bt;
s3c2412_iotiming_getbank(cfg, bt, bank);
}
s3c2412_print_timing("get", timings);
return 0;
}
/* this is in here as it is so small, it doesn't currently warrant a file
* to itself. We expect that any s3c24xx needing this is going to also
* need the iotiming support.
*/
void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
{
struct s3c_cpufreq_board *board = cfg->board;
u32 refresh;
WARN_ON(board == NULL);
/* Reduce both the refresh time (in ns) and the frequency (in MHz)
* down to ensure that we do not overflow 32 bit numbers.
*
* This should work for HCLK up to 133MHz and refresh period up
* to 30usec.
*/
refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
refresh &= ((1 << 16) - 1);
s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
__raw_writel(refresh, S3C2412_REFRESH);
}
arch/arm/plat-s3c24xx/s3c2440-cpufreq.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
*
* Copyright (c) 2006,2008,2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@simtec.co.uk>
*
* S3C2440/S3C2442 CPU Frequency scaling
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
#include <plat/clock.h>
static struct clk *xtal;
static struct clk *fclk;
static struct clk *hclk;
static struct clk *armclk;
/* HDIV: 1, 2, 3, 4, 6, 8 */
static inline int within_khz(unsigned long a, unsigned long b)
{
long diff = a - b;
return (diff >= -1000 && diff <= 1000);
}
/**
* s3c2440_cpufreq_calcdivs - calculate divider settings
* @cfg: The cpu frequency settings.
*
* Calcualte the divider values for the given frequency settings
* specified in @cfg. The values are stored in @cfg for later use
* by the relevant set routine if the request settings can be reached.
*/
int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
{
unsigned int hdiv, pdiv;
unsigned long hclk, fclk, armclk;
unsigned long hclk_max;
fclk = cfg->freq.fclk;
armclk = cfg->freq.armclk;
hclk_max = cfg->max.hclk;
s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
__func__, fclk, armclk, hclk_max);
if (armclk > fclk) {
printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
armclk = fclk;
}
/* if we are in DVS, we need HCLK to be <= ARMCLK */
if (armclk < fclk && armclk < hclk_max)
hclk_max = armclk;
for (hdiv = 1; hdiv < 9; hdiv++) {
if (hdiv == 5 || hdiv == 7)
hdiv++;
hclk = (fclk / hdiv);
if (hclk <= hclk_max || within_khz(hclk, hclk_max))
break;
}
s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
if (hdiv > 8)
goto invalid;
pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
if ((hclk / pdiv) > cfg->max.pclk)
pdiv++;
s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
if (pdiv > 2)
goto invalid;
pdiv *= hdiv;
/* calculate a valid armclk */
if (armclk < hclk)
armclk = hclk;
/* if we're running armclk lower than fclk, this really means
* that the system should go into dvs mode, which means that
* armclk is connected to hclk. */
if (armclk < fclk) {
cfg->divs.dvs = 1;
armclk = hclk;
} else
cfg->divs.dvs = 0;
cfg->freq.armclk = armclk;
/* store the result, and then return */
cfg->divs.h_divisor = hdiv;
cfg->divs.p_divisor = pdiv;
return 0;
invalid:
return -EINVAL;
}
#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
S3C2440_CAMDIVN_HCLK4_HALF)
/**
* s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
* @cfg: The cpu frequency settings.
*
* Set the divisors from the settings in @cfg, which where generated
* during the calculation phase by s3c2440_cpufreq_calcdivs().
*/
static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
{
unsigned long clkdiv, camdiv;
s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
cfg->divs.h_divisor, cfg->divs.p_divisor);
clkdiv = __raw_readl(S3C2410_CLKDIVN);
camdiv = __raw_readl(S3C2440_CAMDIVN);
clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
camdiv &= ~CAMDIVN_HCLK_HALF;
switch (cfg->divs.h_divisor) {
case 1:
clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
break;
case 2:
clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
break;
case 6:
camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
case 3:
clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
break;
case 8:
camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
case 4:
clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
break;
default:
BUG(); /* we don't expect to get here. */
}
if (cfg->divs.p_divisor != cfg->divs.h_divisor)
clkdiv |= S3C2440_CLKDIVN_PDIVN;
/* todo - set pclk. */
/* Write the divisors first with hclk intentionally halved so that
* when we write clkdiv we will under-frequency instead of over. We
* then make a short delay and remove the hclk halving if necessary.
*/
__raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
__raw_writel(clkdiv, S3C2410_CLKDIVN);
ndelay(20);
__raw_writel(camdiv, S3C2440_CAMDIVN);
clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
}
static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
int *divs,
struct cpufreq_frequency_table *table,
size_t table_size)
{
unsigned long freq;
int index = 0;
int div;
for (div = *divs; div > 0; div = *divs++) {
freq = fclk / div;
if (freq > max_hclk && div != 1)
continue;
freq /= 1000; /* table is in kHz */
index = s3c_cpufreq_addfreq(table, index, table_size, freq);
if (index < 0)
break;
}
return index;
}
static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
struct cpufreq_frequency_table *table,
size_t table_size)
{
int ret;
WARN_ON(cfg->info == NULL);
WARN_ON(cfg->board == NULL);
ret = run_freq_for(cfg->info->max.hclk,
cfg->info->max.fclk,
hclk_divs,
table, table_size);
s3c_freq_dbg("%s: returning %d\n", __func__, ret);
return ret;
}
struct s3c_cpufreq_info s3c2440_cpufreq_info = {
.max = {
.fclk = 400000000,
.hclk = 133333333,
.pclk = 66666666,
},
.locktime_m = 300,
.locktime_u = 300,
.locktime_bits = 16,
.name = "s3c244x",
.calc_iotiming = s3c2410_iotiming_calc,
.set_iotiming = s3c2410_iotiming_set,
.get_iotiming = s3c2410_iotiming_get,
.set_fvco = s3c2410_set_fvco,
.set_refresh = s3c2410_cpufreq_setrefresh,
.set_divs = s3c2440_cpufreq_setdivs,
.calc_divs = s3c2440_cpufreq_calcdivs,
.calc_freqtable = s3c2440_cpufreq_calctable,
.resume_clocks = s3c244x_setup_clocks,
.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
};
static int s3c2440_cpufreq_add(struct sys_device *sysdev)
{
xtal = s3c_cpufreq_clk_get(NULL, "xtal");
hclk = s3c_cpufreq_clk_get(NULL, "hclk");
fclk = s3c_cpufreq_clk_get(NULL, "fclk");
armclk = s3c_cpufreq_clk_get(NULL, "armclk");
if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
printk(KERN_ERR "%s: failed to get clocks\n", __func__);
return -ENOENT;
}
return s3c_cpufreq_register(&s3c2440_cpufreq_info);
}
static struct sysdev_driver s3c2440_cpufreq_driver = {
.add = s3c2440_cpufreq_add,
};
static int s3c2440_cpufreq_init(void)
{
return sysdev_driver_register(&s3c2440_sysclass,
&s3c2440_cpufreq_driver);
}
/* arch_initcall adds the clocks we need, so use subsys_initcall. */
subsys_initcall(s3c2440_cpufreq_init);
static struct sysdev_driver s3c2442_cpufreq_driver = {
.add = s3c2440_cpufreq_add,
};
static int s3c2442_cpufreq_init(void)
{
return sysdev_driver_register(&s3c2442_sysclass,
&s3c2442_cpufreq_driver);
}
subsys_initcall(s3c2442_cpufreq_init);
arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c 0 → 100644
View file @ 29c08460
/* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
*
* Copyright (c) 2006,2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@arm.linux.org.uk>
*
* S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
{ .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
{ .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
{ .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
{ .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
{ .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
{ .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
{ .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
{ .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
{ .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
{ .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
{ .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
{ .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
{ .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
{ .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
{ .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
{ .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
{ .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
{ .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
{ .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
{ .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
{ .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
{ .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
{ .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
{ .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
{ .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
{ .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
{ .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
};
static int s3c2440_plls12_add(struct sys_device *dev)
{
struct clk *xtal_clk;
unsigned long xtal;
xtal_clk = clk_get(NULL, "xtal");
if (IS_ERR(xtal_clk))
return PTR_ERR(xtal_clk);
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
if (xtal == 12000000) {
printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
return s3c_plltab_register(s3c2440_plls_12,
ARRAY_SIZE(s3c2440_plls_12));
}
return 0;
}
static struct sysdev_driver s3c2440_plls12_drv = {
.add = s3c2440_plls12_add,
};
static int __init s3c2440_pll_12mhz(void)
{
return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv);
}
arch_initcall(s3c2440_pll_12mhz);
static struct sysdev_driver s3c2442_plls12_drv = {
.add = s3c2440_plls12_add,
};
static int __init s3c2442_pll_12mhz(void)
{
return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
}
arch_initcall(s3c2442_pll_12mhz);
arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c 0 → 100644
View file @ 29c08460
/* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
*
* Copyright (c) 2006-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@arm.linux.org.uk>
*
* S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>
static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
{ .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
{ .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */
{ .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */
{ .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */
{ .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */
{ .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */
{ .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */
{ .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */
{ .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */
{ .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */
{ .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */
{ .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */
{ .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */
{ .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */
{ .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */
{ .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */
{ .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */
{ .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */
{ .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */
{ .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */
{ .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */
{ .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */
{ .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */
{ .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */
{ .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */
{ .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */
{ .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */
{ .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */
{ .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */
{ .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */
{ .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */
{ .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */
{ .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */
{ .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */
{ .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */
{ .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */
{ .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */
{ .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */
{ .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */
{ .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */
{ .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */
{ .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */
{ .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */
{ .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */
{ .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */
{ .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */
{ .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */
{ .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */
{ .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */
{ .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */
{ .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */
{ .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */
{ .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */
{ .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */
{ .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
};
static int s3c2440_plls169344_add(struct sys_device *dev)
{
struct clk *xtal_clk;
unsigned long xtal;
xtal_clk = clk_get(NULL, "xtal");
if (IS_ERR(xtal_clk))
return PTR_ERR(xtal_clk);
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
if (xtal == 169344000) {
printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
return s3c_plltab_register(s3c2440_plls_169344,
ARRAY_SIZE(s3c2440_plls_169344));
}
return 0;
}
static struct sysdev_driver s3c2440_plls169344_drv = {
.add = s3c2440_plls169344_add,
};
static int __init s3c2440_pll_16934400(void)
{
return sysdev_driver_register(&s3c2440_sysclass,
&s3c2440_plls169344_drv);
}
arch_initcall(s3c2440_pll_16934400);
static struct sysdev_driver s3c2442_plls169344_drv = {
.add = s3c2440_plls169344_add,
};
static int __init s3c2442_pll_16934400(void)
{
return sysdev_driver_register(&s3c2442_sysclass,
&s3c2442_plls169344_drv);
}
arch_initcall(s3c2442_pll_16934400);
arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <mach/spi.h>
#include <mach/regs-gpio.h>
void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
int enable)
{
printk(KERN_INFO "%s(%d)\n", __func__, enable);
if (enable) {
s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
} else {
s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPD(10), 1);
s3c2410_gpio_pullup(S3C2410_GPD(9), 1);
s3c2410_gpio_pullup(S3C2410_GPD(8), 1);
}
}
arch/arm/plat-s3c64xx/Kconfig
View file @ 29c08460
......@@ -19,6 +19,7 @@ config PLAT_S3C64XX
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
select S3C_DEV_NAND
select USB_ARCH_HAS_OHCI
help
Base platform code for any Samsung S3C64XX device
......
arch/arm/plat-s3c64xx/Makefile
View file @ 29c08460
......@@ -41,3 +41,4 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o
arch/arm/plat-s3c64xx/s3c6400-clock.c
View file @ 29c08460
......@@ -153,7 +153,7 @@ static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
u32 div;
if (parent < rate)
return rate;
return parent;
div = (parent / rate) - 1;
if (div > armclk_mask)
......@@ -175,7 +175,7 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
div = clk_get_rate(clk->parent) / rate;
val = __raw_readl(S3C_CLK_DIV0);
val &= armclk_mask;
val &= ~armclk_mask;
val |= (div - 1);
__raw_writel(val, S3C_CLK_DIV0);
......
arch/arm/plat-s5pc1xx/Kconfig 0 → 100644
View file @ 29c08460
# arch/arm/plat-s5pc1xx/Kconfig
#
# Copyright 2009 Samsung Electronics Co.
# Byungho Min <bhmin@samsung.com>
#
# Licensed under GPLv2
config PLAT_S5PC1XX
bool
depends on ARCH_S5PC1XX
default y
select PLAT_S3C
select ARM_VIC
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
help
Base platform code for any Samsung S5PC1XX device
if PLAT_S5PC1XX
# Configuration options shared by all S3C64XX implementations
config CPU_S5PC100_INIT
bool
help
Common initialisation code for the S5PC1XX
config CPU_S5PC100_CLOCK
bool
help
Common clock support code for the S5PC1XX
# platform specific device setup
config S5PC100_SETUP_I2C0
bool
default y
help
Common setup code for i2c bus 0.
Note, currently since i2c0 is always compiled, this setup helper
is always compiled with it.
config S5PC100_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
endif
arch/arm/plat-s5pc1xx/Makefile 0 → 100644
View file @ 29c08460
# arch/arm/plat-s5pc1xx/Makefile
#
# Copyright 2009 Samsung Electronics Co.
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n := dummy.o
obj- :=
# Core files
obj-y += dev-uart.o
obj-y += cpu.o
obj-y += irq.o
# CPU support
obj-$(CONFIG_CPU_S5PC100_INIT) += s5pc100-init.o
obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
# Device setup
obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
arch/arm/plat-s5pc1xx/cpu.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s5pc1xx/cpu.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX CPU Support
*
* Based on plat-s3c64xx/cpu.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <asm/mach/map.h>
#include <plat/regs-serial.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/s5pc100.h>
/* table of supported CPUs */
static const char name_s5pc100[] = "S5PC100";
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = 0x43100000,
.idmask = 0xfffff000,
.map_io = s5pc100_map_io,
.init_clocks = s5pc100_init_clocks,
.init_uarts = s5pc100_init_uarts,
.init = s5pc100_init,
.name = name_s5pc100,
},
};
/* minimal IO mapping */
/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */
#define UART_OFFS (S3C_PA_UART & 0xffff)
static struct map_desc s5pc1xx_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5PC1XX_VA_CHIPID,
.pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID),
.length = SZ_16,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_CLK,
.pfn = __phys_to_pfn(S5PC1XX_PA_CLK),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_PWR,
.pfn = __phys_to_pfn(S5PC1XX_PA_PWR),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)(S5PC1XX_VA_UART),
.pfn = __phys_to_pfn(S5PC1XX_PA_UART),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_VIC(0),
.pfn = __phys_to_pfn(S5PC1XX_PA_VIC(0)),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_VIC(1),
.pfn = __phys_to_pfn(S5PC1XX_PA_VIC(1)),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_VIC(2),
.pfn = __phys_to_pfn(S5PC1XX_PA_VIC(2)),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_TIMER,
.pfn = __phys_to_pfn(S5PC1XX_PA_TIMER),
.length = SZ_256,
.type = MT_DEVICE,
},
};
/* read cpu identification code */
void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size)
{
unsigned long idcode;
/* initialise the io descriptors we need for initialisation */
iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc));
iotable_init(mach_desc, size);
idcode = __raw_readl(S5PC1XX_VA_CHIPID);
s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
}
arch/arm/plat-s5pc1xx/dev-uart.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s5pc1xx/dev-uart.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Based on plat-s3c64xx/dev-uart.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/devs.h>
/* Serial port registrations */
/* 64xx uarts are closer together */
static struct resource s5pc1xx_uart0_resource[] = {
[0] = {
.start = S3C_PA_UART0,
.end = S3C_PA_UART0 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX0,
.end = IRQ_S3CUART_RX0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX0,
.end = IRQ_S3CUART_TX0,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR0,
.end = IRQ_S3CUART_ERR0,
.flags = IORESOURCE_IRQ,
}
};
static struct resource s5pc1xx_uart1_resource[] = {
[0] = {
.start = S3C_PA_UART1,
.end = S3C_PA_UART1 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX1,
.end = IRQ_S3CUART_RX1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX1,
.end = IRQ_S3CUART_TX1,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR1,
.end = IRQ_S3CUART_ERR1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource s5pc1xx_uart2_resource[] = {
[0] = {
.start = S3C_PA_UART2,
.end = S3C_PA_UART2 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX2,
.end = IRQ_S3CUART_RX2,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX2,
.end = IRQ_S3CUART_TX2,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR2,
.end = IRQ_S3CUART_ERR2,
.flags = IORESOURCE_IRQ,
},
};
static struct resource s5pc1xx_uart3_resource[] = {
[0] = {
.start = S3C_PA_UART3,
.end = S3C_PA_UART3 + 0x100,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3CUART_RX3,
.end = IRQ_S3CUART_RX3,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_S3CUART_TX3,
.end = IRQ_S3CUART_TX3,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_S3CUART_ERR3,
.end = IRQ_S3CUART_ERR3,
.flags = IORESOURCE_IRQ,
},
};
struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = {
[0] = {
.resources = s5pc1xx_uart0_resource,
.nr_resources = ARRAY_SIZE(s5pc1xx_uart0_resource),
},
[1] = {
.resources = s5pc1xx_uart1_resource,
.nr_resources = ARRAY_SIZE(s5pc1xx_uart1_resource),
},
[2] = {
.resources = s5pc1xx_uart2_resource,
.nr_resources = ARRAY_SIZE(s5pc1xx_uart2_resource),
},
[3] = {
.resources = s5pc1xx_uart3_resource,
.nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource),
},
};
/* uart devices */
static struct platform_device s3c24xx_uart_device0 = {
.id = 0,
};
static struct platform_device s3c24xx_uart_device1 = {
.id = 1,
};
static struct platform_device s3c24xx_uart_device2 = {
.id = 2,
};
static struct platform_device s3c24xx_uart_device3 = {
.id = 3,
};
struct platform_device *s3c24xx_uart_src[4] = {
&s3c24xx_uart_device0,
&s3c24xx_uart_device1,
&s3c24xx_uart_device2,
&s3c24xx_uart_device3,
};
struct platform_device *s3c24xx_uart_devs[4] = {
};
arch/arm/plat-s5pc1xx/include/plat/irqs.h 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX - Common IRQ support
*
* Based on plat-s3c64xx/include/plat/irqs.h
*/
#ifndef __ASM_PLAT_S5PC1XX_IRQS_H
#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__
/* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
* and we don't end up having to do horrible things to the
* standard ISA drivers....
*
* note, since we're using the VICs, our start must be a
* mulitple of 32 to allow the common code to work
*/
#define S3C_IRQ_OFFSET (32)
#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
#define S3C_VIC0_BASE S3C_IRQ(0)
#define S3C_VIC1_BASE S3C_IRQ(32)
#define S3C_VIC2_BASE S3C_IRQ(64)
/* UART interrupts, each UART has 4 intterupts per channel so
* use the space between the ISA and S3C main interrupts. Note, these
* are not in the same order as the S3C24XX series! */
#define IRQ_S3CUART_BASE0 (16)
#define IRQ_S3CUART_BASE1 (20)
#define IRQ_S3CUART_BASE2 (24)
#define IRQ_S3CUART_BASE3 (28)
#define UART_IRQ_RXD (0)
#define UART_IRQ_ERR (1)
#define UART_IRQ_TXD (2)
#define UART_IRQ_MODEM (3)
#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
/* VIC based IRQs */
#define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
#define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
#define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x))
/*
* VIC0: system, DMA, timer
*/
#define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0)
#define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1)
#define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2)
#define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3)
#define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4)
#define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5)
#define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6)
#define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7)
#define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8)
#define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9)
#define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10)
#define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11)
#define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12)
#define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13)
#define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14)
#define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15)
#define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16)
#define IRQ_BATF S5PC1XX_IRQ_VIC0(17)
#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18)
#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19)
#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20)
#define IRQ_TIMER0 S5PC1XX_IRQ_VIC0(21)
#define IRQ_TIMER1 S5PC1XX_IRQ_VIC0(22)
#define IRQ_TIMER2 S5PC1XX_IRQ_VIC0(23)
#define IRQ_TIMER3 S5PC1XX_IRQ_VIC0(24)
#define IRQ_TIMER4 S5PC1XX_IRQ_VIC0(25)
#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26)
#define IRQ_WDT S5PC1XX_IRQ_VIC0(27)
#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28)
#define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29)
#define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30)
/*
* VIC1: ARM, power, memory, connectivity
*/
#define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0)
#define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1)
#define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2)
#define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3)
#define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4)
#define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5)
#define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6)
#define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7)
#define IRQ_NFC S5PC1XX_IRQ_VIC1(8)
#define IRQ_CFC S5PC1XX_IRQ_VIC1(9)
#define IRQ_UART0 S5PC1XX_IRQ_VIC1(10)
#define IRQ_UART1 S5PC1XX_IRQ_VIC1(11)
#define IRQ_UART2 S5PC1XX_IRQ_VIC1(12)
#define IRQ_UART3 S5PC1XX_IRQ_VIC1(13)
#define IRQ_IIC S5PC1XX_IRQ_VIC1(14)
#define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15)
#define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16)
#define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17)
#define IRQ_IRDA S5PC1XX_IRQ_VIC1(18)
#define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19)
#define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20)
#define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21)
#define IRQ_HSITX S5PC1XX_IRQ_VIC1(22)
#define IRQ_UHOST S5PC1XX_IRQ_VIC1(23)
#define IRQ_OTG S5PC1XX_IRQ_VIC1(24)
#define IRQ_MSM S5PC1XX_IRQ_VIC1(25)
#define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26)
#define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27)
#define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28)
#define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29)
#define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30)
/*
* VIC2: multimedia, audio, security
*/
#define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0)
#define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1)
#define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2)
#define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3)
#define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4)
#define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5)
#define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6)
#define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7)
#define IRQ_JPEG S5PC1XX_IRQ_VIC2(8)
#define IRQ_2D S5PC1XX_IRQ_VIC2(9)
#define IRQ_3D S5PC1XX_IRQ_VIC2(10)
#define IRQ_MIXER S5PC1XX_IRQ_VIC2(11)
#define IRQ_HDMI S5PC1XX_IRQ_VIC2(12)
#define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13)
#define IRQ_MFC S5PC1XX_IRQ_VIC2(14)
#define IRQ_TVENC S5PC1XX_IRQ_VIC2(15)
#define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16)
#define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17)
#define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18)
#define IRQ_AC97 S5PC1XX_IRQ_VIC2(19)
#define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20)
#define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21)
#define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22)
#define IRQ_ADC S5PC1XX_IRQ_VIC2(23)
#define IRQ_PENDN S5PC1XX_IRQ_VIC2(24)
#define IRQ_TC IRQ_PENDN
#define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25)
#define IRQ_CG S5PC1XX_IRQ_VIC2(26)
#define IRQ_SEC S5PC1XX_IRQ_VIC2(27)
#define IRQ_SECRX S5PC1XX_IRQ_VIC2(28)
#define IRQ_SECTX S5PC1XX_IRQ_VIC2(29)
#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30)
#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31)
#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1)
#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
#define IRQ_EINT(x) S3C_EINT(x)
#define NR_IRQS (IRQ_EINT(31)+1)
#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
arch/arm/plat-s5pc1xx/include/plat/pll.h 0 → 100644
View file @ 29c08460
/* arch/arm/plat-s5pc1xx/include/plat/pll.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX PLL code
*
* Based on plat-s3c64xx/include/plat/pll.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
#define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
#define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
#define S5P_PLL_MDIV_SHIFT (16)
#define S5P_PLL_PDIV_SHIFT (8)
#define S5P_PLL_SDIV_SHIFT (0)
#include <asm/div64.h>
static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
u32 pllcon)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK;
pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK;
sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
arch/arm/plat-s5pc1xx/include/plat/regs-clock.h 0 → 100644
View file @ 29c08460
/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_CLOCK_H
#define __PLAT_REGS_CLOCK_H __FILE__
#define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x))
#define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00)
#define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04)
#define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08)
#define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C)
#define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100)
#define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104)
#define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108)
#define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C)
#define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200)
#define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204)
#define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208)
#define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C)
#define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300)
#define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304)
#define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308)
#define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C)
#define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310)
#define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400)
#define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500)
#define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504)
#define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508)
#define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520)
#define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524)
#define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528)
#define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C)
#define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530)
#define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534)
#define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540)
#define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560)
#define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564)
#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200)
#define S5PC1XX_EPLL_EN (1<<31)
#define S5PC1XX_EPLL_MASK 0xffffffff
#define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
/* CLKSRC0 */
#define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0)
#define S5PC1XX_CLKSRC0_APLL_SHIFT (0)
#define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4)
#define S5PC1XX_CLKSRC0_MPLL_SHIFT (4)
#define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8)
#define S5PC1XX_CLKSRC0_EPLL_SHIFT (8)
#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12)
#define S5PC100_CLKSRC0_HPLL_SHIFT (12)
#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16)
#define S5PC100_CLKSRC0_AMMUX_SHIFT (16)
#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20)
#define S5PC100_CLKSRC0_HREF_SHIFT (20)
#define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24)
#define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24)
/* CLKSRC1 */
#define S5PC100_CLKSRC1_UART_MASK (0x1<<0)
#define S5PC100_CLKSRC1_UART_SHIFT (0)
#define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4)
#define S5PC100_CLKSRC1_SPI0_SHIFT (4)
#define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8)
#define S5PC100_CLKSRC1_SPI1_SHIFT (8)
#define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12)
#define S5PC100_CLKSRC1_SPI2_SHIFT (12)
#define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16)
#define S5PC100_CLKSRC1_IRDA_SHIFT (16)
#define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20)
#define S5PC100_CLKSRC1_UHOST_SHIFT (20)
#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
#define S5PC100_CLKSRC1_CLK48M_SHIFT (24)
/* CLKSRC2 */
#define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0)
#define S5PC100_CLKSRC2_MMC0_SHIFT (0)
#define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4)
#define S5PC100_CLKSRC2_MMC1_SHIFT (4)
#define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8)
#define S5PC100_CLKSRC2_MMC2_SHIFT (8)
#define S5PC100_CLKSRC2_LCD_MASK (0x3<<12)
#define S5PC100_CLKSRC2_LCD_SHIFT (12)
#define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16)
#define S5PC100_CLKSRC2_FIMC0_SHIFT (16)
#define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20)
#define S5PC100_CLKSRC2_FIMC1_SHIFT (20)
#define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24)
#define S5PC100_CLKSRC2_FIMC2_SHIFT (24)
#define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28)
#define S5PC100_CLKSRC2_MIXER_SHIFT (28)
/* CLKSRC3 */
#define S5PC100_CLKSRC3_PWI_MASK (0x3<<0)
#define S5PC100_CLKSRC3_PWI_SHIFT (0)
#define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4)
#define S5PC100_CLKSRC3_HCLKD2_SHIFT (4)
#define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8)
#define S5PC100_CLKSRC3_I2SD2_SHIFT (8)
#define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12)
#define S5PC100_CLKSRC3_AUDIO0_SHIFT (12)
#define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16)
#define S5PC100_CLKSRC3_AUDIO1_SHIFT (16)
#define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20)
#define S5PC100_CLKSRC3_AUDIO2_SHIFT (20)
#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24)
#define S5PC100_CLKSRC3_SPDIF_SHIFT (24)
/* CLKDIV0 */
#define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0)
#define S5PC1XX_CLKDIV0_APLL_SHIFT (0)
#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
#define S5PC100_CLKDIV0_ARM_SHIFT (4)
#define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
#define S5PC100_CLKDIV0_D0_SHIFT (8)
#define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12)
#define S5PC100_CLKDIV0_PCLKD0_SHIFT (12)
#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
/* CLKDIV1 */
#define S5PC100_CLKDIV1_AM_MASK (0x7<<0)
#define S5PC100_CLKDIV1_AM_SHIFT (0)
#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
#define S5PC100_CLKDIV1_MPLL_SHIFT (4)
#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
#define S5PC100_CLKDIV1_MPLL2_SHIFT (8)
#define S5PC100_CLKDIV1_D1_MASK (0x7<<12)
#define S5PC100_CLKDIV1_D1_SHIFT (12)
#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
#define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20)
#define S5PC100_CLKDIV1_ONENAND_SHIFT (20)
#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
#define S5PC100_CLKDIV1_CAM_SHIFT (24)
/* CLKDIV2 */
#define S5PC100_CLKDIV2_UART_MASK (0x7<<0)
#define S5PC100_CLKDIV2_UART_SHIFT (0)
#define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4)
#define S5PC100_CLKDIV2_SPI0_SHIFT (4)
#define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8)
#define S5PC100_CLKDIV2_SPI1_SHIFT (8)
#define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12)
#define S5PC100_CLKDIV2_SPI2_SHIFT (12)
#define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16)
#define S5PC100_CLKDIV2_IRDA_SHIFT (16)
#define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20)
#define S5PC100_CLKDIV2_UHOST_SHIFT (20)
/* CLKDIV3 */
#define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0)
#define S5PC100_CLKDIV3_MMC0_SHIFT (0)
#define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4)
#define S5PC100_CLKDIV3_MMC1_SHIFT (4)
#define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8)
#define S5PC100_CLKDIV3_MMC2_SHIFT (8)
#define S5PC100_CLKDIV3_LCD_MASK (0xf<<12)
#define S5PC100_CLKDIV3_LCD_SHIFT (12)
#define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16)
#define S5PC100_CLKDIV3_FIMC0_SHIFT (16)
#define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20)
#define S5PC100_CLKDIV3_FIMC1_SHIFT (20)
#define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24)
#define S5PC100_CLKDIV3_FIMC2_SHIFT (24)
#define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28)
#define S5PC100_CLKDIV3_HDMI_SHIFT (28)
/* CLKDIV4 */
#define S5PC100_CLKDIV4_PWI_MASK (0x7<<0)
#define S5PC100_CLKDIV4_PWI_SHIFT (0)
#define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4)
#define S5PC100_CLKDIV4_HCLKD2_SHIFT (4)
#define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8)
#define S5PC100_CLKDIV4_I2SD2_SHIFT (8)
#define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12)
#define S5PC100_CLKDIV4_AUDIO0_SHIFT (12)
#define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16)
#define S5PC100_CLKDIV4_AUDIO1_SHIFT (16)
#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20)
#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20)
/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
#define S5PC100_CLKGATE_D00_INTC (1<<0)
#define S5PC100_CLKGATE_D00_TZIC (1<<1)
#define S5PC100_CLKGATE_D00_CFCON (1<<2)
#define S5PC100_CLKGATE_D00_MDMA (1<<3)
#define S5PC100_CLKGATE_D00_G2D (1<<4)
#define S5PC100_CLKGATE_D00_SECSS (1<<5)
#define S5PC100_CLKGATE_D00_CSSYS (1<<6)
/* HCLKD0/PCLKD0 Clock Gate 1 Registers */
#define S5PC100_CLKGATE_D01_DMC (1<<0)
#define S5PC100_CLKGATE_D01_SROMC (1<<1)
#define S5PC100_CLKGATE_D01_ONENAND (1<<2)
#define S5PC100_CLKGATE_D01_NFCON (1<<3)
#define S5PC100_CLKGATE_D01_INTMEM (1<<4)
#define S5PC100_CLKGATE_D01_EBI (1<<5)
/* PCLKD0 Clock Gate 2 Registers */
#define S5PC100_CLKGATE_D02_SECKEY (1<<1)
#define S5PC100_CLKGATE_D02_SDM (1<<2)
/* HCLKD1/PCLKD1 Clock Gate 0 Registers */
#define S5PC100_CLKGATE_D10_PDMA0 (1<<0)
#define S5PC100_CLKGATE_D10_PDMA1 (1<<1)
#define S5PC100_CLKGATE_D10_USBHOST (1<<2)
#define S5PC100_CLKGATE_D10_USBOTG (1<<3)
#define S5PC100_CLKGATE_D10_MODEMIF (1<<4)
#define S5PC100_CLKGATE_D10_HSMMC0 (1<<5)
#define S5PC100_CLKGATE_D10_HSMMC1 (1<<6)
#define S5PC100_CLKGATE_D10_HSMMC2 (1<<7)
/* HCLKD1/PCLKD1 Clock Gate 1 Registers */
#define S5PC100_CLKGATE_D11_LCD (1<<0)
#define S5PC100_CLKGATE_D11_ROTATOR (1<<1)
#define S5PC100_CLKGATE_D11_FIMC0 (1<<2)
#define S5PC100_CLKGATE_D11_FIMC1 (1<<3)
#define S5PC100_CLKGATE_D11_FIMC2 (1<<4)
#define S5PC100_CLKGATE_D11_JPEG (1<<5)
#define S5PC100_CLKGATE_D11_DSI (1<<6)
#define S5PC100_CLKGATE_D11_CSI (1<<7)
#define S5PC100_CLKGATE_D11_G3D (1<<8)
/* HCLKD1/PCLKD1 Clock Gate 2 Registers */
#define S5PC100_CLKGATE_D12_TV (1<<0)
#define S5PC100_CLKGATE_D12_VP (1<<1)
#define S5PC100_CLKGATE_D12_MIXER (1<<2)
#define S5PC100_CLKGATE_D12_HDMI (1<<3)
#define S5PC100_CLKGATE_D12_MFC (1<<4)
/* HCLKD1/PCLKD1 Clock Gate 3 Registers */
#define S5PC100_CLKGATE_D13_CHIPID (1<<0)
#define S5PC100_CLKGATE_D13_GPIO (1<<1)
#define S5PC100_CLKGATE_D13_APC (1<<2)
#define S5PC100_CLKGATE_D13_IEC (1<<3)
#define S5PC100_CLKGATE_D13_PWM (1<<6)
#define S5PC100_CLKGATE_D13_SYSTIMER (1<<7)
#define S5PC100_CLKGATE_D13_WDT (1<<8)
#define S5PC100_CLKGATE_D13_RTC (1<<9)
/* HCLKD1/PCLKD1 Clock Gate 4 Registers */
#define S5PC100_CLKGATE_D14_UART0 (1<<0)
#define S5PC100_CLKGATE_D14_UART1 (1<<1)
#define S5PC100_CLKGATE_D14_UART2 (1<<2)
#define S5PC100_CLKGATE_D14_UART3 (1<<3)
#define S5PC100_CLKGATE_D14_IIC (1<<4)
#define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5)
#define S5PC100_CLKGATE_D14_SPI0 (1<<6)
#define S5PC100_CLKGATE_D14_SPI1 (1<<7)
#define S5PC100_CLKGATE_D14_SPI2 (1<<8)
#define S5PC100_CLKGATE_D14_IRDA (1<<9)
#define S5PC100_CLKGATE_D14_CCAN0 (1<<10)
#define S5PC100_CLKGATE_D14_CCAN1 (1<<11)
#define S5PC100_CLKGATE_D14_HSITX (1<<12)
#define S5PC100_CLKGATE_D14_HSIRX (1<<13)
/* HCLKD1/PCLKD1 Clock Gate 5 Registers */
#define S5PC100_CLKGATE_D15_IIS0 (1<<0)
#define S5PC100_CLKGATE_D15_IIS1 (1<<1)
#define S5PC100_CLKGATE_D15_IIS2 (1<<2)
#define S5PC100_CLKGATE_D15_AC97 (1<<3)
#define S5PC100_CLKGATE_D15_PCM0 (1<<4)
#define S5PC100_CLKGATE_D15_PCM1 (1<<5)
#define S5PC100_CLKGATE_D15_SPDIF (1<<6)
#define S5PC100_CLKGATE_D15_TSADC (1<<7)
#define S5PC100_CLKGATE_D15_KEYIF (1<<8)
#define S5PC100_CLKGATE_D15_CG (1<<9)
/* HCLKD2 Clock Gate 0 Registers */
#define S5PC100_CLKGATE_D20_HCLKD2 (1<<0)
#define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
/* Special Clock Gate 0 Registers */
#define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0)
#define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1)
#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
#define S5PC100_CLKGATE_SCLK0_UART (1<<3)
#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
#define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5)
#define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6)
#define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7)
#define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8)
#define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9)
#define S5PC100_CLKGATE_SCLK0_IRDA (1<<10)
#define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11)
#define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12)
#define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13)
#define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14)
#define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15)
#define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16)
#define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17)
/* Special Clock Gate 1 Registers */
#define S5PC100_CLKGATE_SCLK1_LCD (1<<0)
#define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1)
#define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2)
#define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3)
#define S5PC100_CLKGATE_SCLK1_TV54 (1<<4)
#define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5)
#define S5PC100_CLKGATE_SCLK1_MIXER (1<<6)
#define S5PC100_CLKGATE_SCLK1_HDMI (1<<7)
#define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8)
#define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9)
#define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10)
#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
#define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
/* register for power management */
#define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000)
#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004)
#define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010)
#define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014)
#define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018)
#define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C)
#define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100)
#define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104)
#define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108)
#define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110)
#define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114)
#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200)
#define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300)
#define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304)
#define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308)
#define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400)
#define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404)
#define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408)
#define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C)
#define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410)
#define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414)
#define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418)
#define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C)
#define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500)
#define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504)
#define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508)
#define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C)
#define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510)
#define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514)
#define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518)
#define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C)
#define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520)
#define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600)
#define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604)
#define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608)
#define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C)
#define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610)
#define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614)
#define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618)
#define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C)
#define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620)
#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700)
#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704)
#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708)
#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C)
#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710)
#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714)
#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718)
#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C)
#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724)
#define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000)
#define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008)
#define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100)
#define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104)
#define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200)
#define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300)
#define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304)
#define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308)
#define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400)
#define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414)
#define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420)
#define S5PC100_CFG_WFI_CLEAN (~(3<<5))
#define S5PC100_CFG_WFI_IDLE (1<<5)
#define S5PC100_CFG_WFI_STOP (2<<5)
#define S5PC100_CFG_WFI_SLEEP (3<<5)
#define S5PC100_OTHER_SYS_INT 24
#define S5PC100_OTHER_STA_TYPE 23
#define STA_TYPE_EXPON 0
#define STA_TYPE_SFR 1
#define S5PC100_PWR_STA_EXP_SCALE 0
#define S5PC100_PWR_STA_CNT 4
#define S5PC100_PWR_STABLE_COUNT 85500
#define S5PC100_SLEEP_CFG_OSC_EN 0
/* OTHERS Resgister */
#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
/* MIPI D-PHY Control Register 0 */
#define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1)
#define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0)
#endif /* _PLAT_REGS_CLOCK_H */
arch/arm/plat-s5pc1xx/include/plat/s5pc100.h 0 → 100644
View file @ 29c08460
/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Header file for s5pc100 cpu support
*
* Based on plat-s3c64xx/include/plat/s3c6400.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Common init code for S5PC100 related SoCs */
extern int s5pc100_init(void);
extern void s5pc100_map_io(void);
extern void s5pc100_init_clocks(int xtal);
extern int s5pc100_register_baseclocks(unsigned long xtal);
extern void s5pc100_init_irq(void);
extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s5pc100_register_clocks(void);
extern void s5pc100_setup_clocks(void);
extern struct sysdev_class s5pc100_sysclass;
#define s5pc100_init_uarts s5pc100_common_init_uarts
/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
extern struct clk clk_hpll;
extern struct clk clk_hd0;
extern struct clk clk_pd0;
extern struct clk clk_54m;
extern struct clk clk_dout_mpll2;
extern void s5pc1xx_register_clocks(void);
extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable);
extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable);
/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
extern struct platform_device s3c_device_g2d;
extern struct platform_device s3c_device_g3d;
extern struct platform_device s3c_device_vpp;
extern struct platform_device s3c_device_tvenc;
extern struct platform_device s3c_device_tvscaler;
extern struct platform_device s3c_device_rotator;
extern struct platform_device s3c_device_jpeg;
extern struct platform_device s3c_device_onenand;
extern struct platform_device s3c_device_usb_otghcd;
extern struct platform_device s3c_device_keypad;
extern struct platform_device s3c_device_ts;
extern struct platform_device s3c_device_g3d;
extern struct platform_device s3c_device_smc911x;
extern struct platform_device s3c_device_fimc0;
extern struct platform_device s3c_device_fimc1;
extern struct platform_device s3c_device_mfc;
extern struct platform_device s3c_device_ac97;
extern struct platform_device s3c_device_fimc0;
extern struct platform_device s3c_device_fimc1;
extern struct platform_device s3c_device_fimc2;
arch/arm/plat-s5pc1xx/irq.c 0 → 100644
View file @ 29c08460
/* arch/arm/plat-s5pc1xx/irq.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX - Interrupt handling
*
* Based on plat-s3c64xx/irq.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/regs-timer.h>
#include <plat/cpu.h>
/* Timer interrupt handling */
static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
{
generic_handle_irq(sub_irq);
}
static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER0);
}
static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER1);
}
static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER2);
}
static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER3);
}
static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_timer(irq, IRQ_TIMER4);
}
/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
static void s3c_irq_timer_mask(unsigned int irq)
{
u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
reg &= 0x1f; /* mask out pending interrupts */
reg &= ~(1 << (irq - IRQ_TIMER0));
__raw_writel(reg, S3C64XX_TINT_CSTAT);
}
static void s3c_irq_timer_unmask(unsigned int irq)
{
u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
reg &= 0x1f; /* mask out pending interrupts */
reg |= 1 << (irq - IRQ_TIMER0);
__raw_writel(reg, S3C64XX_TINT_CSTAT);
}
static void s3c_irq_timer_ack(unsigned int irq)
{
u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
reg &= 0x1f;
reg |= (1 << 5) << (irq - IRQ_TIMER0);
__raw_writel(reg, S3C64XX_TINT_CSTAT);
}
static struct irq_chip s3c_irq_timer = {
.name = "s3c-timer",
.mask = s3c_irq_timer_mask,
.unmask = s3c_irq_timer_unmask,
.ack = s3c_irq_timer_ack,
};
struct uart_irq {
void __iomem *regs;
unsigned int base_irq;
unsigned int parent_irq;
};
/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
* are consecutive when looking up the interrupt in the demux routines.
*/
static struct uart_irq uart_irqs[] = {
[0] = {
.regs = (void *)S3C_VA_UART0,
.base_irq = IRQ_S3CUART_BASE0,
.parent_irq = IRQ_UART0,
},
[1] = {
.regs = (void *)S3C_VA_UART1,
.base_irq = IRQ_S3CUART_BASE1,
.parent_irq = IRQ_UART1,
},
[2] = {
.regs = (void *)S3C_VA_UART2,
.base_irq = IRQ_S3CUART_BASE2,
.parent_irq = IRQ_UART2,
},
[3] = {
.regs = (void *)S3C_VA_UART3,
.base_irq = IRQ_S3CUART_BASE3,
.parent_irq = IRQ_UART3,
},
};
static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
{
struct uart_irq *uirq = get_irq_chip_data(irq);
return uirq->regs;
}
static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
{
return irq & 3;
}
/* UART interrupt registers, not worth adding to seperate include header */
#define S3C64XX_UINTP 0x30
#define S3C64XX_UINTSP 0x34
#define S3C64XX_UINTM 0x38
static void s3c_irq_uart_mask(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
u32 reg;
reg = __raw_readl(regs + S3C64XX_UINTM);
reg |= (1 << bit);
__raw_writel(reg, regs + S3C64XX_UINTM);
}
static void s3c_irq_uart_maskack(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
u32 reg;
reg = __raw_readl(regs + S3C64XX_UINTM);
reg |= (1 << bit);
__raw_writel(reg, regs + S3C64XX_UINTM);
__raw_writel(1 << bit, regs + S3C64XX_UINTP);
}
static void s3c_irq_uart_unmask(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
u32 reg;
reg = __raw_readl(regs + S3C64XX_UINTM);
reg &= ~(1 << bit);
__raw_writel(reg, regs + S3C64XX_UINTM);
}
static void s3c_irq_uart_ack(unsigned int irq)
{
void __iomem *regs = s3c_irq_uart_base(irq);
unsigned int bit = s3c_irq_uart_bit(irq);
__raw_writel(1 << bit, regs + S3C64XX_UINTP);
}
static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
{
struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
int base = uirq->base_irq;
if (pend & (1 << 0))
generic_handle_irq(base);
if (pend & (1 << 1))
generic_handle_irq(base + 1);
if (pend & (1 << 2))
generic_handle_irq(base + 2);
if (pend & (1 << 3))
generic_handle_irq(base + 3);
}
static struct irq_chip s3c_irq_uart = {
.name = "s3c-uart",
.mask = s3c_irq_uart_mask,
.unmask = s3c_irq_uart_unmask,
.mask_ack = s3c_irq_uart_maskack,
.ack = s3c_irq_uart_ack,
};
static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
{
void __iomem *reg_base = uirq->regs;
unsigned int irq;
int offs;
/* mask all interrupts at the start. */
__raw_writel(0xf, reg_base + S3C64XX_UINTM);
for (offs = 0; offs < 3; offs++) {
irq = uirq->base_irq + offs;
set_irq_chip(irq, &s3c_irq_uart);
set_irq_chip_data(irq, uirq);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
}
void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
{
int i;
int uart, irq;
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */
for (i = 0; i < num; i++)
vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET),
vic_valid[i], 0);
/* add the timer sub-irqs */
set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0);
set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1);
set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2);
set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3);
set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4);
for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
set_irq_chip(irq, &s3c_irq_timer);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
s5pc1xx_uart_irq(&uart_irqs[uart]);
}
arch/arm/plat-s5pc1xx/s5pc100-clock.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c
*
* Copyright 2009 Samsung Electronics, Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 based common clock support
*
* Based on plat-s3c64xx/s3c6400-clock.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/cpu-freq.h>
#include <plat/regs-clock.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/devs.h>
#include <plat/s5pc100.h>
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* ext_xtal_mux for want of an actual name from the manual.
*/
static struct clk clk_ext_xtal_mux = {
.name = "ext_xtal",
.id = -1,
};
#define clk_fin_apll clk_ext_xtal_mux
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux
#define clk_fin_hpll clk_ext_xtal_mux
#define clk_fout_mpll clk_mpll
struct clk_sources {
unsigned int nr_sources;
struct clk **sources;
};
struct clksrc_clk {
struct clk clk;
unsigned int mask;
unsigned int shift;
struct clk_sources *sources;
unsigned int divider_shift;
void __iomem *reg_divider;
void __iomem *reg_source;
};
static int clk_default_setrate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 1;
}
struct clk clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
};
static int clk_48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S5PC1XX_CLK_SRC1);
if (enable)
val |= S5PC100_CLKSRC1_CLK48M_MASK;
else
val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
__raw_writel(val, S5PC1XX_CLK_SRC1);
local_irq_restore(flags);
return 0;
}
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
struct clk clk_54m = {
.name = "clk_54m",
.id = -1,
.rate = 54000000,
};
struct clk clk_hpll = {
.name = "hpll",
.id = -1,
};
struct clk clk_hd0 = {
.name = "hclkd0",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_pd0 = {
.name = "pclkd0",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
static int s5pc1xx_clk_gate(void __iomem *reg,
struct clk *clk,
int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
}
static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
}
static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
}
static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
}
static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
}
static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
}
static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
}
static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
}
static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
}
static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
}
int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
}
int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
}
static struct clk init_clocks_disable[] = {
{
.name = "dsi",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_DSI,
}, {
.name = "csi",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_CSI,
}, {
.name = "ccan0",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
}, {
.name = "ccan1",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
}, {
.name = "keypad",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
}, {
.name = "hclkd2",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_clk_d20_ctrl,
.ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
}, {
.name = "iis-d2",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_clk_d20_ctrl,
.ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
}, {
.name = "otg",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
},
};
static struct clk init_clocks[] = {
/* System1 (D0_0) devices */
{
.name = "intc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_INTC,
}, {
.name = "tzic",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_TZIC,
}, {
.name = "cf-ata",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_CFCON,
}, {
.name = "mdma",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_MDMA,
}, {
.name = "g2d",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_G2D,
}, {
.name = "secss",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_SECSS,
}, {
.name = "cssys",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
},
/* Memory (D0_1) devices */
{
.name = "dmc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_DMC,
}, {
.name = "sromc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_SROMC,
}, {
.name = "onenand",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
}, {
.name = "nand",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_NFCON,
}, {
.name = "intmem",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
}, {
.name = "ebi",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_EBI,
},
/* System2 (D0_2) devices */
{
.name = "seckey",
.id = -1,
.parent = &clk_pd0,
.enable = s5pc1xx_clk_d02_ctrl,
.ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
}, {
.name = "sdm",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d02_ctrl,
.ctrlbit = S5PC100_CLKGATE_D02_SDM,
},
/* File (D1_0) devices */
{
.name = "pdma0",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
}, {
.name = "pdma1",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
}, {
.name = "modem",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
},
/* Multimedia1 (D1_1) devices */
{
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_LCD,
}, {
.name = "rotator",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
}, {
.name = "fimc",
.id = 0,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
}, {
.name = "fimc",
.id = 1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
}, {
.name = "fimc",
.id = 2,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
}, {
.name = "jpeg",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_JPEG,
}, {
.name = "g3d",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_G3D,
},
/* Multimedia2 (D1_2) devices */
{
.name = "tv",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_TV,
}, {
.name = "vp",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_VP,
}, {
.name = "mixer",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_MIXER,
}, {
.name = "hdmi",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_HDMI,
}, {
.name = "mfc",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_MFC,
},
/* System (D1_3) devices */
{
.name = "chipid",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_GPIO,
}, {
.name = "apc",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_APC,
}, {
.name = "iec",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_IEC,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_PWM,
}, {
.name = "systimer",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_WDT,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_RTC,
},
/* Connectivity (D1_4) devices */
{
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART3,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_IIC,
}, {
.name = "hdmi-i2c",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
}, {
.name = "spi",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI1,
}, {
.name = "spi",
.id = 2,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI2,
}, {
.name = "irda",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_IRDA,
}, {
.name = "hsitx",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HSITX,
}, {
.name = "hsirx",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
},
/* Audio (D1_5) devices */
{
.name = "iis",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS0,
}, {
.name = "iis",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS1,
}, {
.name = "iis",
.id = 2,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS2,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_AC97,
}, {
.name = "pcm",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_PCM0,
}, {
.name = "pcm",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_PCM1,
}, {
.name = "spdif",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_TSADC,
}, {
.name = "keyif",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
}, {
.name = "cg",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_CG,
},
/* Audio (D2_0) devices: all disabled */
/* Special Clocks 1 */
{
.name = "sclk_hpm",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC1XX_CLKGATE_SCLK0_HPM,
}, {
.name = "sclk_onenand",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
}, {
.name = "sclk_spi_48",
.id = 0,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
}, {
.name = "sclk_spi_48",
.id = 1,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
}, {
.name = "sclk_spi_48",
.id = 2,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
}, {
.name = "sclk_mmc_48",
.id = 0,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
}, {
.name = "sclk_mmc_48",
.id = 1,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
}, {
.name = "sclk_mmc_48",
.id = 2,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
},
/* Special Clocks 2 */
{
.name = "sclk_tv_54",
.id = -1,
.parent = &clk_54m,
.enable = s5pc1xx_sclk1_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK1_TV54,
}, {
.name = "sclk_vdac_54",
.id = -1,
.parent = &clk_54m,
.enable = s5pc1xx_sclk1_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK1_VDAC54,
}, {
.name = "sclk_spdif",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_sclk1_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK1_SPDIF,
},
};
void __init s5pc1xx_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
clkp = init_clocks;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}
static struct clk clk_fout_apll = {
.name = "fout_apll",
.id = -1,
};
static struct clk *clk_src_apll_list[] = {
[0] = &clk_fin_apll,
[1] = &clk_fout_apll,
};
static struct clk_sources clk_src_apll = {
.sources = clk_src_apll_list,
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
};
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.shift = S5PC1XX_CLKSRC0_APLL_SHIFT,
.mask = S5PC1XX_CLKSRC0_APLL_MASK,
.sources = &clk_src_apll,
.reg_source = S5PC1XX_CLK_SRC0,
};
static struct clk clk_fout_epll = {
.name = "fout_epll",
.id = -1,
};
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
[1] = &clk_fout_epll,
};
static struct clk_sources clk_src_epll = {
.sources = clk_src_epll_list,
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.shift = S5PC1XX_CLKSRC0_EPLL_SHIFT,
.mask = S5PC1XX_CLKSRC0_EPLL_MASK,
.sources = &clk_src_epll,
.reg_source = S5PC1XX_CLK_SRC0,
};
static struct clk *clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_fout_mpll,
};
static struct clk_sources clk_src_mpll = {
.sources = clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
},
.shift = S5PC1XX_CLKSRC0_MPLL_SHIFT,
.mask = S5PC1XX_CLKSRC0_MPLL_MASK,
.sources = &clk_src_mpll,
.reg_source = S5PC1XX_CLK_SRC0,
};
static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned long clkdiv;
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
return rate;
}
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
.get_rate = s5pc1xx_clk_doutmpll_get_rate,
};
static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned long clkdiv;
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
return rate;
}
struct clk clk_dout_mpll2 = {
.name = "dout_mpll2",
.id = -1,
.parent = &clk_mout_mpll.clk,
.get_rate = s5pc1xx_clk_doutmpll2_get_rate,
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
NULL,
NULL
};
static struct clk_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static inline struct clksrc_clk *to_clksrc(struct clk *clk)
{
return container_of(clk, struct clksrc_clk, clk);
}
static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
{
struct clksrc_clk *sclk = to_clksrc(clk);
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv = __raw_readl(sclk->reg_divider);
clkdiv >>= sclk->divider_shift;
clkdiv &= 0xf;
clkdiv++;
rate /= clkdiv;
return rate;
}
static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
{
struct clksrc_clk *sclk = to_clksrc(clk);
void __iomem *reg = sclk->reg_divider;
unsigned int div;
u32 val;
rate = clk_round_rate(clk, rate);
div = clk_get_rate(clk->parent) / rate;
if (div > 16)
return -EINVAL;
val = __raw_readl(reg);
val &= ~(0xf << sclk->shift);
val |= (div - 1) << sclk->shift;
__raw_writel(val, reg);
return 0;
}
static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
{
struct clksrc_clk *sclk = to_clksrc(clk);
struct clk_sources *srcs = sclk->sources;
u32 clksrc = __raw_readl(sclk->reg_source);
int src_nr = -1;
int ptr;
for (ptr = 0; ptr < srcs->nr_sources; ptr++)
if (srcs->sources[ptr] == parent) {
src_nr = ptr;
break;
}
if (src_nr >= 0) {
clksrc &= ~sclk->mask;
clksrc |= src_nr << sclk->shift;
__raw_writel(clksrc, sclk->reg_source);
return 0;
}
return -EINVAL;
}
static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
unsigned long rate)
{
unsigned long parent_rate = clk_get_rate(clk->parent);
int div;
if (rate > parent_rate)
rate = parent_rate;
else {
div = rate / parent_rate;
if (div == 0)
div = 1;
if (div > 16)
div = 16;
rate = parent_rate / div;
}
return rate;
}
static struct clksrc_clk clk_uart_uclk1 = {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
.enable = s5pc1xx_sclk0_ctrl,
.set_parent = s5pc1xx_setparent_clksrc,
.get_rate = s5pc1xx_getrate_clksrc,
.set_rate = s5pc1xx_setrate_clksrc,
.round_rate = s5pc1xx_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC1_UART_SHIFT,
.mask = S5PC100_CLKSRC1_UART_MASK,
.sources = &clkset_uart,
.divider_shift = S5PC100_CLKDIV2_UART_SHIFT,
.reg_divider = S5PC1XX_CLK_DIV2,
.reg_source = S5PC1XX_CLK_SRC1,
};
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_uart_uclk1,
};
static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
{
struct clk_sources *srcs = clk->sources;
u32 clksrc = __raw_readl(clk->reg_source);
clksrc &= clk->mask;
clksrc >>= clk->shift;
if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
printk(KERN_ERR "%s: bad source %d\n",
clk->clk.name, clksrc);
return;
}
clk->clk.parent = srcs->sources[clksrc];
printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
clk->clk.name, clk->clk.parent->name, clksrc,
clk_get_rate(&clk->clk));
}
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
void __init_or_cpufreq s5pc100_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long armclk;
unsigned long hclkd0;
unsigned long hclk;
unsigned long pclkd0;
unsigned long pclk;
unsigned long apll;
unsigned long mpll;
unsigned long hpll;
unsigned long epll;
unsigned int ptr;
u32 clkdiv0, clkdiv1;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
__func__, clkdiv0, clkdiv1);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
apll, mpll, epll, hpll);
armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n",
armclk, hclkd0, pclkd0, hclk, pclk);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_h.rate = hclk;
clk_p.rate = pclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s5pc1xx_set_clksrc(init_parents[ptr]);
}
static struct clk *clks[] __initdata = {
&clk_ext_xtal_mux,
&clk_mout_epll.clk,
&clk_fout_epll,
&clk_mout_mpll.clk,
&clk_dout_mpll,
&clk_uart_uclk1.clk,
&clk_ext,
&clk_epll,
&clk_27m,
&clk_48m,
&clk_54m,
};
void __init s5pc100_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
clkp = clks[ptr];
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clk_mpll.parent = &clk_mout_mpll.clk;
clk_epll.parent = &clk_mout_epll.clk;
}
arch/arm/plat-s5pc1xx/s5pc100-init.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - CPU initialisation (common with other S5PC1XX chips)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s5pc100.h>
/* uart registration process */
void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
/* The driver name is s3c6400-uart to reuse s3c6400_serial_drv */
s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no);
}
arch/arm/plat-s5pc1xx/setup-i2c0.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Base S5PC1XX I2C bus 0 gpio configuration
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <plat/iic.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
/* Pin configuration would be needed */
}
arch/arm/plat-s5pc1xx/setup-i2c1.c 0 → 100644
View file @ 29c08460
/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Base S5PC1XX I2C bus 1 gpio configuration
*
* Based on plat-s3c64xx/setup-i2c1.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <plat/iic.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
/* Pin configuration would be needed */
}
drivers/hwmon/Kconfig
View file @ 29c08460
......@@ -702,6 +702,23 @@ config SENSORS_SHT15
This driver can also be built as a module. If so, the module
will be called sht15.
config SENSORS_S3C
tristate "S3C24XX/S3C64XX Inbuilt ADC"
depends on ARCH_S3C2410 || ARCH_S3C64XX
help
If you say yes here you get support for the on-board ADCs of
the Samsung S3C24XX or S3C64XX series of SoC
This driver can also be built as a module. If so, the module
will be called s3c-hwmo.
config SENSORS_S3C_RAW
bool "Include raw channel attributes in sysfs"
depends on SENSORS_S3C
help
Say Y here if you want to include raw copies of all the ADC
channels in sysfs.
config SENSORS_SIS5595
tristate "Silicon Integrated Systems Corp. SiS5595"
depends on PCI
......
drivers/hwmon/Makefile
View file @ 29c08460
......@@ -76,6 +76,7 @@ obj-$(CONFIG_SENSORS_MAX6650) += max6650.o
obj-$(CONFIG_SENSORS_PC87360) += pc87360.o
obj-$(CONFIG_SENSORS_PC87427) += pc87427.o
obj-$(CONFIG_SENSORS_PCF8591) += pcf8591.o
obj-$(CONFIG_SENSORS_S3C) += s3c-hwmon.o
obj-$(CONFIG_SENSORS_SHT15) += sht15.o
obj-$(CONFIG_SENSORS_SIS5595) += sis5595.o
obj-$(CONFIG_SENSORS_SMSC47B397)+= smsc47b397.o
......
drivers/hwmon/s3c-hwmon.c 0 → 100644
View file @ 29c08460
/* linux/drivers/hwmon/s3c-hwmon.c
*
* Copyright (C) 2005, 2008, 2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX/S3C64XX ADC hwmon support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <plat/adc.h>
#include <plat/hwmon.h>
struct s3c_hwmon_attr {
struct sensor_device_attribute in;
struct sensor_device_attribute label;
char in_name[12];
char label_name[12];
};
/**
* struct s3c_hwmon - ADC hwmon client information
* @lock: Access lock to serialise the conversions.
* @client: The client we registered with the S3C ADC core.
* @hwmon_dev: The hwmon device we created.
* @attr: The holders for the channel attributes.
*/
struct s3c_hwmon {
struct semaphore lock;
struct s3c_adc_client *client;
struct device *hwmon_dev;
struct s3c_hwmon_attr attrs[8];
};
/**
* s3c_hwmon_read_ch - read a value from a given adc channel.
* @dev: The device.
* @hwmon: Our state.
* @channel: The channel we're reading from.
*
* Read a value from the @channel with the proper locking and sleep until
* either the read completes or we timeout awaiting the ADC core to get
* back to us.
*/
static int s3c_hwmon_read_ch(struct device *dev,
struct s3c_hwmon *hwmon, int channel)
{
int ret;
ret = down_interruptible(&hwmon->lock);
if (ret < 0)
return ret;
dev_dbg(dev, "reading channel %d\n", channel);
ret = s3c_adc_read(hwmon->client, channel);
up(&hwmon->lock);
return ret;
}
#ifdef CONFIG_SENSORS_S3C_RAW
/**
* s3c_hwmon_show_raw - show a conversion from the raw channel number.
* @dev: The device that the attribute belongs to.
* @attr: The attribute being read.
* @buf: The result buffer.
*
* This show deals with the raw attribute, registered for each possible
* ADC channel. This does a conversion and returns the raw (un-scaled)
* value returned from the hardware.
*/
static ssize_t s3c_hwmon_show_raw(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct s3c_hwmon *adc = platform_get_drvdata(to_platform_device(dev));
struct sensor_device_attribute *sa = to_sensor_dev_attr(attr);
int ret;
ret = s3c_hwmon_read_ch(dev, adc, sa->index);
return (ret < 0) ? ret : snprintf(buf, PAGE_SIZE, "%d\n", ret);
}
#define DEF_ADC_ATTR(x) \
static SENSOR_DEVICE_ATTR(adc##x##_raw, S_IRUGO, s3c_hwmon_show_raw, NULL, x)
DEF_ADC_ATTR(0);
DEF_ADC_ATTR(1);
DEF_ADC_ATTR(2);
DEF_ADC_ATTR(3);
DEF_ADC_ATTR(4);
DEF_ADC_ATTR(5);
DEF_ADC_ATTR(6);
DEF_ADC_ATTR(7);
static struct attribute *s3c_hwmon_attrs[9] = {
&sensor_dev_attr_adc0_raw.dev_attr.attr,
&sensor_dev_attr_adc1_raw.dev_attr.attr,
&sensor_dev_attr_adc2_raw.dev_attr.attr,
&sensor_dev_attr_adc3_raw.dev_attr.attr,
&sensor_dev_attr_adc4_raw.dev_attr.attr,
&sensor_dev_attr_adc5_raw.dev_attr.attr,
&sensor_dev_attr_adc6_raw.dev_attr.attr,
&sensor_dev_attr_adc7_raw.dev_attr.attr,
NULL,
};
static struct attribute_group s3c_hwmon_attrgroup = {
.attrs = s3c_hwmon_attrs,
};
static inline int s3c_hwmon_add_raw(struct device *dev)
{
return sysfs_create_group(&dev->kobj, &s3c_hwmon_attrgroup);
}
static inline void s3c_hwmon_remove_raw(struct device *dev)
{
sysfs_remove_group(&dev->kobj, &s3c_hwmon_attrgroup);
}
#else
static inline int s3c_hwmon_add_raw(struct device *dev) { return 0; }
static inline void s3c_hwmon_remove_raw(struct device *dev) { }
#endif /* CONFIG_SENSORS_S3C_RAW */
/**
* s3c_hwmon_ch_show - show value of a given channel
* @dev: The device that the attribute belongs to.
* @attr: The attribute being read.
* @buf: The result buffer.
*
* Read a value from the ADC and scale it before returning it to the
* caller. The scale factor is gained from the channel configuration
* passed via the platform data when the device was registered.
*/
static ssize_t s3c_hwmon_ch_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sen_attr = to_sensor_dev_attr(attr);
struct s3c_hwmon *hwmon = platform_get_drvdata(to_platform_device(dev));
struct s3c_hwmon_pdata *pdata = dev->platform_data;
struct s3c_hwmon_chcfg *cfg;
int ret;
cfg = pdata->in[sen_attr->index];
ret = s3c_hwmon_read_ch(dev, hwmon, sen_attr->index);
if (ret < 0)
return ret;
ret *= cfg->mult;
ret = DIV_ROUND_CLOSEST(ret, cfg->div);
return snprintf(buf, PAGE_SIZE, "%d\n", ret);
}
/**
* s3c_hwmon_label_show - show label name of the given channel.
* @dev: The device that the attribute belongs to.
* @attr: The attribute being read.
* @buf: The result buffer.
*
* Return the label name of a given channel
*/
static ssize_t s3c_hwmon_label_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sen_attr = to_sensor_dev_attr(attr);
struct s3c_hwmon_pdata *pdata = dev->platform_data;
struct s3c_hwmon_chcfg *cfg;
cfg = pdata->in[sen_attr->index];
return snprintf(buf, PAGE_SIZE, "%s\n", cfg->name);
}
/**
* s3c_hwmon_create_attr - create hwmon attribute for given channel.
* @dev: The device to create the attribute on.
* @cfg: The channel configuration passed from the platform data.
* @channel: The ADC channel number to process.
*
* Create the scaled attribute for use with hwmon from the specified
* platform data in @pdata. The sysfs entry is handled by the routine
* s3c_hwmon_ch_show().
*
* The attribute name is taken from the configuration data if present
* otherwise the name is taken by concatenating in_ with the channel
* number.
*/
static int s3c_hwmon_create_attr(struct device *dev,
struct s3c_hwmon_chcfg *cfg,
struct s3c_hwmon_attr *attrs,
int channel)
{
struct sensor_device_attribute *attr;
int ret;
snprintf(attrs->in_name, sizeof(attrs->in_name), "in%d_input", channel);
attr = &attrs->in;
attr->index = channel;
attr->dev_attr.attr.name = attrs->in_name;
attr->dev_attr.attr.mode = S_IRUGO;
attr->dev_attr.attr.owner = THIS_MODULE;
attr->dev_attr.show = s3c_hwmon_ch_show;
ret = device_create_file(dev, &attr->dev_attr);
if (ret < 0) {
dev_err(dev, "failed to create input attribute\n");
return ret;
}
/* if this has a name, add a label */
if (cfg->name) {
snprintf(attrs->label_name, sizeof(attrs->label_name),
"in%d_label", channel);
attr = &attrs->label;
attr->index = channel;
attr->dev_attr.attr.name = attrs->label_name;
attr->dev_attr.attr.mode = S_IRUGO;
attr->dev_attr.attr.owner = THIS_MODULE;
attr->dev_attr.show = s3c_hwmon_label_show;
ret = device_create_file(dev, &attr->dev_attr);
if (ret < 0) {
device_remove_file(dev, &attrs->in.dev_attr);
dev_err(dev, "failed to create label attribute\n");
}
}
return ret;
}
static void s3c_hwmon_remove_attr(struct device *dev,
struct s3c_hwmon_attr *attrs)
{
device_remove_file(dev, &attrs->in.dev_attr);
device_remove_file(dev, &attrs->label.dev_attr);
}
/**
* s3c_hwmon_probe - device probe entry.
* @dev: The device being probed.
*/
static int __devinit s3c_hwmon_probe(struct platform_device *dev)
{
struct s3c_hwmon_pdata *pdata = dev->dev.platform_data;
struct s3c_hwmon *hwmon;
int ret = 0;
int i;
if (!pdata) {
dev_err(&dev->dev, "no platform data supplied\n");
return -EINVAL;
}
hwmon = kzalloc(sizeof(struct s3c_hwmon), GFP_KERNEL);
if (hwmon == NULL) {
dev_err(&dev->dev, "no memory\n");
return -ENOMEM;
}
platform_set_drvdata(dev, hwmon);
init_MUTEX(&hwmon->lock);
/* Register with the core ADC driver. */
hwmon->client = s3c_adc_register(dev, NULL, NULL, 0);
if (IS_ERR(hwmon->client)) {
dev_err(&dev->dev, "cannot register adc\n");
ret = PTR_ERR(hwmon->client);
goto err_mem;
}
/* add attributes for our adc devices. */
ret = s3c_hwmon_add_raw(&dev->dev);
if (ret)
goto err_registered;
/* register with the hwmon core */
hwmon->hwmon_dev = hwmon_device_register(&dev->dev);
if (IS_ERR(hwmon->hwmon_dev)) {
dev_err(&dev->dev, "error registering with hwmon\n");
ret = PTR_ERR(hwmon->hwmon_dev);
goto err_raw_attribute;
}
for (i = 0; i < ARRAY_SIZE(pdata->in); i++) {
if (!pdata->in[i])
continue;
if (pdata->in[i]->mult >= 0x10000)
dev_warn(&dev->dev,
"channel %d multiplier too large\n",
i);
ret = s3c_hwmon_create_attr(&dev->dev, pdata->in[i],
&hwmon->attrs[i], i);
if (ret) {
dev_err(&dev->dev,
"error creating channel %d\n", i);
for (i--; i >= 0; i--)
s3c_hwmon_remove_attr(&dev->dev,
&hwmon->attrs[i]);
goto err_hwmon_register;
}
}
return 0;
err_hwmon_register:
hwmon_device_unregister(hwmon->hwmon_dev);
err_raw_attribute:
s3c_hwmon_remove_raw(&dev->dev);
err_registered:
s3c_adc_release(hwmon->client);
err_mem:
kfree(hwmon);
return ret;
}
static int __devexit s3c_hwmon_remove(struct platform_device *dev)
{
struct s3c_hwmon *hwmon = platform_get_drvdata(dev);
int i;
s3c_hwmon_remove_raw(&dev->dev);
for (i = 0; i < ARRAY_SIZE(hwmon->attrs); i++)
s3c_hwmon_remove_attr(&dev->dev, &hwmon->attrs[i]);
hwmon_device_unregister(hwmon->hwmon_dev);
s3c_adc_release(hwmon->client);
return 0;
}
static struct platform_driver s3c_hwmon_driver = {
.driver = {
.name = "s3c-hwmon",
.owner = THIS_MODULE,
},
.probe = s3c_hwmon_probe,
.remove = __devexit_p(s3c_hwmon_remove),
};
static int __init s3c_hwmon_init(void)
{
return platform_driver_register(&s3c_hwmon_driver);
}
static void __exit s3c_hwmon_exit(void)
{
platform_driver_unregister(&s3c_hwmon_driver);
}
module_init(s3c_hwmon_init);
module_exit(s3c_hwmon_exit);
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_DESCRIPTION("S3C ADC HWMon driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:s3c-hwmon");
drivers/serial/Kconfig
View file @ 29c08460
......@@ -459,7 +459,7 @@ config SERIAL_SAMSUNG_UARTS
int
depends on ARM && PLAT_S3C
default 2 if ARCH_S3C2400
default 4 if ARCH_S3C64XX || CPU_S3C2443
default 4 if ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443
default 3
help
Select the number of available UART ports for the Samsung S3C
......@@ -533,6 +533,13 @@ config SERIAL_S3C6400
Serial port support for the Samsung S3C6400 and S3C6410
SoCs
config SERIAL_S5PC100
tristate "Samsung S5PC100 Serial port support"
depends on SERIAL_SAMSUNG && CPU_S5PC100
default y
help
Serial port support for the Samsung S5PC100 SoCs
config SERIAL_MAX3100
tristate "MAX3100 support"
depends on SPI
......
drivers/serial/Makefile
View file @ 29c08460
......@@ -43,6 +43,7 @@ obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o
obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
obj-$(CONFIG_SERIAL_MUX) += mux.o
......
include/linux/amba/pl093.h 0 → 100644
View file @ 29c08460
/* linux/amba/pl093.h
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* AMBA PL093 SSMC (synchronous static memory controller)
* See DDI0236.pdf (r0p4) for more details
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */
/* Offsets for SMBxxxxRy registers */
#define SMBIDCYR (0x00)
#define SMBWSTRDR (0x04)
#define SMBWSTWRR (0x08)
#define SMBWSTOENR (0x0C)
#define SMBWSTWENR (0x10)
#define SMBCR (0x14)
#define SMBSR (0x18)
#define SMBWSTBRDR (0x1C)
/* Masks for SMB registers */
#define IDCY_MASK (0xf)
#define WSTRD_MASK (0xf)
#define WSTWR_MASK (0xf)
#define WSTOEN_MASK (0xf)
#define WSTWEN_MASK (0xf)
/* Notes from datasheet:
* WSTOEN <= WSTRD
* WSTWEN <= WSTWR
*
* WSTOEN is not used with nWAIT
*/
/* SMBCR bit definitions */
#define SMBCR_BIWRITEEN (1 << 21)
#define SMBCR_ADDRVALIDWRITEEN (1 << 20)
#define SMBCR_SYNCWRITE (1 << 17)
#define SMBCR_BMWRITE (1 << 16)
#define SMBCR_WRAPREAD (1 << 14)
#define SMBCR_BIREADEN (1 << 13)
#define SMBCR_ADDRVALIDREADEN (1 << 12)
#define SMBCR_SYNCREAD (1 << 9)
#define SMBCR_BMREAD (1 << 8)
#define SMBCR_SMBLSPOL (1 << 6)
#define SMBCR_WP (1 << 3)
#define SMBCR_WAITEN (1 << 2)
#define SMBCR_WAITPOL (1 << 1)
#define SMBCR_RBLE (1 << 0)
#define SMBCR_BURSTLENWRITE_MASK (3 << 18)
#define SMBCR_BURSTLENWRITE_4 (0 << 18)
#define SMBCR_BURSTLENWRITE_8 (1 << 18)
#define SMBCR_BURSTLENWRITE_RESERVED (2 << 18)
#define SMBCR_BURSTLENWRITE_CONTINUOUS (3 << 18)
#define SMBCR_BURSTLENREAD_MASK (3 << 10)
#define SMBCR_BURSTLENREAD_4 (0 << 10)
#define SMBCR_BURSTLENREAD_8 (1 << 10)
#define SMBCR_BURSTLENREAD_16 (2 << 10)
#define SMBCR_BURSTLENREAD_CONTINUOUS (3 << 10)
#define SMBCR_MW_MASK (3 << 4)
#define SMBCR_MW_8BIT (0 << 4)
#define SMBCR_MW_16BIT (1 << 4)
#define SMBCR_MW_M32BIT (2 << 4)
/* SSMC status registers */
#define SSMCCSR (0x200)
#define SSMCCR (0x204)
#define SSMCITCR (0x208)
#define SSMCITIP (0x20C)
#define SSMCITIOP (0x210)
sound/soc/s3c24xx/s3c24xx-ac97.h
View file @ 29c08460
......@@ -20,12 +20,6 @@
#define AC_CMD_ADDR(x) (x << 16)
#define AC_CMD_DATA(x) (x & 0xffff)
#ifdef CONFIG_CPU_S3C2440
#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
#else
#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
#endif
extern struct snd_soc_dai s3c2443_ac97_dai[];
#endif /*S3C24XXAC97_H_*/
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