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Commit 2a17bb8c authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'devicetree-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:
 "DT Bindings:

   - Drop duplicate devices in trivial-devices.yaml

   - Add a common serial peripheral device schema and reference it in
     serial device schemas.

   - Convert nxp,lpc1850-wdt, zii,rave-wdt, ti,davinci-wdt,
     snps,archs-pct, fsl,bcsr, fsl,fpga-qixis-i2c, fsl,fpga-qixis,
     fsl,cpm-enet, fsl,cpm-mdio, fsl,ucc-hdlc, maxim,ds26522,
     aspeed,ast2400-cvic, aspeed,ast2400-vic, fsl,ftm-timer,
     ti,davinci-timer, fsl,rcpm, and qcom,ebi2 to DT schema

   - Add support for rockchip,rk3576-wdt, qcom,apss-wdt-sa8255p,
     fsl,imx8qm-irqsteer, qcom,pm6150-vib, qcom,sa8255p-pdc,
     isil,isl69260, ti,tps546d24, and lpc32xx DMA mux

   - Drop duplicate nvidia,tegra186-ccplex-cluster.yaml and
     mediatek,mt6795-sys-clock.yaml

   - Add arm,gic ESPI and EPPI interrupt type specifiers

   - Add another batch of legacy compatible strings which we have no
     intention of documenting

   - Add dmas/dma-names properties to FSL lcdif

   - Fix wakeup-source reference to m8921-keypad.yaml

   - Treewide fixes of typos in bindings

  DT Core:

   - Update dtc/libfdt to upstream version v1.7.0-95-gbcd02b523429

   - More conversions to scoped iterators and __free() initializer

   - Handle overflows in address resources on 32-bit systems

   - Extend extracting compatible strings in sources from function
     parameters

   - Use of_property_present() in DT unittest

   - Clean-up of_irq_to_resource() to use helpers

   - Support #msi-cells=<0> in of_msi_get_domain()

   - Improve the kerneldoc for of_property_match_string()

   - kselftest: Ignore nodes that have ancestors disabled"

* tag 'devicetree-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (59 commits)
  dt-bindings: watchdog: Add rockchip,rk3576-wdt compatible
  dt-bindings: cpu: Drop duplicate nvidia,tegra186-ccplex-cluster.yaml
  dt-bindings: clock: mediatek: Drop duplicate mediatek,mt6795-sys-clock.yaml
  of/irq: Use helper to define resources
  of/irq: Make use of irq_get_trigger_type()
  dt-bindings: clk: vc5: Make SD/OE pin configuration properties not required
  drivers/of: Improve documentation for match_string
  of: property: Do some clean up with use of __free()
  dt-bindings: watchdog: qcom-wdt: document support on SA8255p
  dt-bindings: interrupt-controller: fsl,irqsteer: Document fsl,imx8qm-irqsteer
  dt-bindings: interrupt-controller: arm,gic: add ESPI and EPPI specifiers
  dt-bindings: dma: Add lpc32xx DMA mux binding
  dt-bindings: trivial-devices: Drop duplicate "maxim,max1237"
  dt-bindings: trivial-devices: Drop duplicate LM75 compatible devices
  dt-bindings: trivial-devices: Deprecate "ad,ad7414"
  dt-bindings: trivial-devices: Drop incorrect and duplicate at24 compatibles
  dt-bindings: wakeup-source: update reference to m8921-keypad.yaml
  dt-bindings: interrupt-controller: qcom-pdc: document support for SA8255p
  dt-bindings: Fix various typos
  of: address: Unify resource bounds overflow checking
  ...
parents 19a519ca 0c36680c
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Showing with 1756 additions and 927 deletions
Documentation/devicetree/bindings/arc/archs-pct.txt deleted 100644 → 0
View file @ 19a519ca
* ARC HS Performance Counters
The ARC HS can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
are 100+ hardware conditions dynamically mapped to up to 32 counters.
It also supports overflow interrupts.
Required properties:
- compatible : should contain
"snps,archs-pct"
Example:
pmu {
compatible = "snps,archs-pct";
};
Documentation/devicetree/bindings/arc/snps,archs-pct.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arc/snps,archs-pct.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARC HS Performance Counters
maintainers:
- Aryabhatta Dey <aryabhattadey35@gmail.com>
description:
The ARC HS can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
are 100+ hardware conditions dynamically mapped to up to 32 counters.
It also supports overflow interrupts.
properties:
compatible:
const: snps,archs-pct
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
additionalProperties: false
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
View file @ 2a17bb8c
......@@ -17,7 +17,7 @@ description: |
The Coresight dummy source component is for the specific coresight source
devices kernel don't have permission to access or configure. For some SOCs,
there would be Coresight source trace components on sub-processor which
are conneted to AP processor via debug bus. For these devices, a dummy driver
are connected to AP processor via debug bus. For these devices, a dummy driver
is needed to register them as Coresight source devices, so that paths can be
created in the driver. It provides Coresight API for operations on dummy
source devices, such as enabling and disabling them. It also provides the
......
Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
View file @ 2a17bb8c
......@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Corstone1000
maintainers:
- Vishnu Banavath <vishnu.banavath@arm.com>
- Rui Miguel Silva <rui.silva@linaro.org>
- Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
- Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
description: |+
ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
......
Documentation/devicetree/bindings/cpu/nvidia,tegra186-ccplex-cluster.yaml → Documentation/devicetree/bindings/board/fsl,bcsr.yaml
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cpu/nvidia,tegra186-ccplex-cluster.yaml#
$id: http://devicetree.org/schemas/board/fsl,bcsr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 CCPLEX Cluster
title: Board Control and Status
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nvidia,tegra186-ccplex-cluster
enum:
- fsl,mpc8360mds-bcsr
reg:
maxItems: 1
nvidia,bpmp:
description: phandle to the BPMP used to query CPU frequency tables
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: false
required:
- compatible
- reg
- nvidia,bpmp
additionalProperties: false
examples:
- |
ccplex@e000000 {
compatible = "nvidia,tegra186-ccplex-cluster";
reg = <0x0e000000 0x400000>;
nvidia,bpmp = <&bpmp>;
board@f8000000 {
compatible = "fsl,mpc8360mds-bcsr";
reg = <0xf8000000 0x8000>;
};
Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale on-board FPGA connected on I2C bus
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,bsc9132qds-fpga
- const: fsl,fpga-qixis-i2c
- items:
- enum:
- fsl,ls1028aqds-fpga
- fsl,lx2160aqds-fpga
- const: fsl,fpga-qixis-i2c
- const: simple-mfd
interrupts:
maxItems: 1
reg:
maxItems: 1
mux-controller:
$ref: /schemas/mux/reg-mux.yaml
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
board-control@66 {
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
reg = <0x66>;
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
board-control@66 {
compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
"simple-mfd";
reg = <0x66>;
mux-controller {
compatible = "reg-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
};
};
};
Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale on-board FPGA/CPLD
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- items:
- const: fsl,p1022ds-fpga
- const: fsl,fpga-ngpixis
- items:
- enum:
- fsl,ls1088aqds-fpga
- fsl,ls1088ardb-fpga
- fsl,ls2080aqds-fpga
- fsl,ls2080ardb-fpga
- const: fsl,fpga-qixis
- items:
- enum:
- fsl,ls1043aqds-fpga
- fsl,ls1043ardb-fpga
- fsl,ls1046aqds-fpga
- fsl,ls1046ardb-fpga
- fsl,ls208xaqds-fpga
- const: fsl,fpga-qixis
- const: simple-mfd
- enum:
- fsl,ls1043ardb-cpld
- fsl,ls1046ardb-cpld
- fsl,t1040rdb-cpld
- fsl,t1042rdb-cpld
- fsl,t1042rdb_pi-cpld
interrupts:
maxItems: 1
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
maxItems: 1
patternProperties:
'^mdio-mux@[a-f0-9,]+$':
$ref: /schemas/net/mdio-mux-mmioreg.yaml
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
board-control@3 {
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0x30>;
interrupt-parent = <&mpic>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW 0 0>;
};
- |
board-control@3 {
compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
reg = <0x3 0x10000>;
};
Documentation/devicetree/bindings/board/fsl-board.txt deleted 100644 → 0
View file @ 19a519ca
Freescale Reference Board Bindings
This document describes device tree bindings for various devices that
exist on some Freescale reference boards.
* Board Control and Status (BCSR)
Required properties:
- compatible : Should be "fsl,<board>-bcsr"
- reg : Offset and length of the register set for the device
Example:
bcsr@f8000000 {
compatible = "fsl,mpc8360mds-bcsr";
reg = <f8000000 8000>;
};
* Freescale on-board FPGA
This is the memory-mapped registers for on board FPGA.
Required properties:
- compatible: should be a board-specific string followed by a string
indicating the type of FPGA. Example:
"fsl,<board>-fpga", "fsl,fpga-pixis", or
"fsl,<board>-fpga", "fsl,fpga-qixis"
- reg: should contain the address and the length of the FPGA register set.
Optional properties:
- interrupts: should specify event (wakeup) IRQ.
Example (P1022DS):
board-control@3,0 {
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
interrupt-parent = <&mpic>;
interrupts = <8 8 0 0>;
};
Example (LS2080A-RDB):
cpld@3,0 {
compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
reg = <0x3 0 0x10000>;
};
* Freescale on-board FPGA connected on I2C bus
Some Freescale boards like BSC9132QDS have on board FPGA connected on
the i2c bus.
Required properties:
- compatible: Should be a board-specific string followed by a string
indicating the type of FPGA. Example:
"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
- reg: Should contain the address of the FPGA
Example:
fpga: fpga@66 {
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
reg = <0x66>;
};
* Freescale on-board CPLD
Some Freescale boards like T1040RDB have an on board CPLD connected.
Required properties:
- compatible: Should be a board-specific string like "fsl,<board>-cpld"
Example:
"fsl,t1040rdb-cpld", "fsl,t1042rdb-cpld", "fsl,t1042rdb_pi-cpld"
- reg: should describe CPLD registers
Example:
cpld@3,0 {
compatible = "fsl,t1040rdb-cpld";
reg = <3 0 0x300>;
};
Documentation/devicetree/bindings/bus/qcom,ebi2.txt deleted 100644 → 0
View file @ 19a519ca
Qualcomm External Bus Interface 2 (EBI2)
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
external memory (such as NAND or other memory-mapped peripherals) whereas
LCDC handles LCD displays.
As it says it connects devices to an external bus interface, meaning address
lines (up to 9 address lines so can only address 1KiB external memory space),
data lines (16 bits), OE (output enable), ADV (address valid, used on some
NOR flash memories), WE (write enable). This on top of 6 different chip selects
(CS0 thru CS5) so that in theory 6 different devices can be connected.
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
and the bus can only come out on these pins, however if some of the pins are
unused they can be left unconnected or remuxed to be used as GPIO or in some
cases other orthogonal functions as well.
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
The chip selects have the following memory range assignments. This region of
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
Chip Select Physical address base
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
August 6, 2012 contains some incomplete documentation of the EBI2.
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
We have not been able to figure out which bit fields these correspond to
in the hardware, or what valid values exist. The current hypothesis is that
this is something just used on the FAST chip selects and that the SLOW
chip selects are understood fully. There is also a "byte device enable"
flag somewhere for 8bit memories.
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
unclear what this means, if they are mutually exclusive or can be used
together, or if some chip selects are hardwired to be FAST and others are SLOW
by design.
The XMEM registers are totally undocumented but could be partially decoded
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
similar register layout, see: http://www.cypress.com/file/105771/download
Required properties:
- compatible: should be one of:
"qcom,msm8660-ebi2"
"qcom,apq8060-ebi2"
- #address-cells: should be <2>: the first cell is the chipselect,
the second cell is the offset inside the memory range
- #size-cells: should be <1>
- ranges: should be set to:
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
- reg: two ranges of registers: EBI2 config and XMEM config areas
- reg-names: should be "ebi2", "xmem"
- clocks: two clocks, EBI_2X and EBI
- clock-names: should be "ebi2x", "ebi2"
Optional subnodes:
- Nodes inside the EBI2 will be considered device nodes.
The following optional properties are properties that can be tagged onto
any device subnode. We are assuming that there can be only ONE device per
chipselect subnode, else the properties will become ambiguous.
Optional properties arrays for SLOW chip selects:
- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
drive the data bus after OE is de-asserted, in order to avoid contention on
the data bus. They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
value is actually 1, so a value of 0 will still yield 1 recovery cycle.
- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
inserted after every write minimum 1. The data out is driven from the time
WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
stays active for 1 extra cycle etc. Valid values 0 thru 15.
- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
the first write to a page or burst memory. Valid values 0 thru 255.
- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
first read to a page or burst memory. Valid values 0 thru 255.
- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
cycle. Valid values 0 thru 15.
- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
cycle. Valid values 0 thru 15.
Optional properties arrays for FAST chip selects:
- qcom,xmem-address-hold-enable: this is a boolean property stating that we
shall hold the address for an extra cycle to meet hold time requirements
with ADV assertion.
- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
assertion, with respect to the cycle where ADV (address valid) is asserted.
2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
read transfer. For a single read transfer this will be the time from CS
assertion to OE assertion. Valid values 0 thru 15.
Example:
ebi2@1a100000 {
compatible = "qcom,apq8060-ebi2";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
reg-names = "ebi2", "xmem";
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
clock-names = "ebi2x", "ebi2";
/* Make sure to set up the pin control for the EBI2 */
pinctrl-names = "default";
pinctrl-0 = <&foo_ebi2_pins>;
foo-ebi2@2,0 {
compatible = "foo";
reg = <2 0x0 0x100>;
(...)
qcom,xmem-recovery-cycles = <0>;
qcom,xmem-write-hold-cycles = <3>;
qcom,xmem-write-delta-cycles = <31>;
qcom,xmem-read-delta-cycles = <28>;
qcom,xmem-write-wait-cycles = <9>;
qcom,xmem-read-wait-cycles = <9>;
};
};
Documentation/devicetree/bindings/bus/qcom,ebi2.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm External Bus Interface 2 (EBI2)
description: |
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
external memory (such as NAND or other memory-mapped peripherals) whereas
LCDC handles LCD displays.
As it says it connects devices to an external bus interface, meaning address
lines (up to 9 address lines so can only address 1KiB external memory space),
data lines (16 bits), OE (output enable), ADV (address valid, used on some
NOR flash memories), WE (write enable). This on top of 6 different chip selects
(CS0 thru CS5) so that in theory 6 different devices can be connected.
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
and the bus can only come out on these pins, however if some of the pins are
unused they can be left unconnected or remuxed to be used as GPIO or in some
cases other orthogonal functions as well.
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
The chip selects have the following memory range assignments. This region of
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
Chip Select Physical address base
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
August 6, 2012 contains some incomplete documentation of the EBI2.
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
We have not been able to figure out which bit fields these correspond to
in the hardware, or what valid values exist. The current hypothesis is that
this is something just used on the FAST chip selects and that the SLOW
chip selects are understood fully. There is also a "byte device enable"
flag somewhere for 8bit memories.
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
unclear what this means, if they are mutually exclusive or can be used
together, or if some chip selects are hardwired to be FAST and others are SLOW
by design.
The XMEM registers are totally undocumented but could be partially decoded
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
similar register layout, see: http://www.cypress.com/file/105771/download
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
enum:
- qcom,apq8060-ebi2
- qcom,msm8660-ebi2
reg:
items:
- description: EBI2 config region
- description: XMEM config region
reg-names:
items:
- const: ebi2
- const: xmem
ranges: true
clocks:
items:
- description: EBI_2X clock
- description: EBI clock
clock-names:
items:
- const: ebi2x
- const: ebi2
'#address-cells':
const: 2
'#size-cells':
const: 1
required:
- compatible
- reg
- reg-names
- ranges
- clocks
- clock-names
- '#address-cells'
- '#size-cells'
patternProperties:
"^.*@[0-5],[0-9a-f]+$":
type: object
additionalProperties: true
properties:
reg:
maxItems: 1
# SLOW chip selects
qcom,xmem-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The time the memory continues to drive the data bus after OE
is de-asserted, in order to avoid contention on the data bus.
They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Minimum value is
actually 1, so a value of 0 will still yield 1 recovery cycle.
minimum: 0
maximum: 15
qcom,xmem-write-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The extra cycles inserted after every write minimum 1. The
data out is driven from the time WE is asserted until CS is
asserted. With a hold of 1 (value = 0), the CS stays active
for 1 extra cycle, etc.
minimum: 0
maximum: 15
qcom,xmem-write-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for write cycles inserted for the first
write to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-read-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for read cycles inserted for the first
read to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-write-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every write access.
minimum: 0
maximum: 15
qcom,xmem-read-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every read access.
minimum: 0
maximum: 15
# FAST chip selects
qcom,xmem-address-hold-enable:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Holds the address for an extra cycle to meet hold time
requirements with ADV assertion, when set to 1.
enum: [ 0, 1 ]
qcom,xmem-adv-to-oe-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of cycles elapsed before an OE assertion, with
respect to the cycle where ADV (address valid) is asserted.
minimum: 0
maximum: 3
qcom,xmem-read-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The length in cycles of the first segment of a read transfer.
For a single read transfer this will be the time from CS
assertion to OE assertion.
minimum: 0
maximum: 15
required:
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
external-bus@1a100000 {
compatible = "qcom,msm8660-ebi2";
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
reg-names = "ebi2", "xmem";
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
clock-names = "ebi2x", "ebi2";
#address-cells = <2>;
#size-cells = <1>;
ethernet@2,0 {
compatible = "smsc,lan9221", "smsc,lan9115";
reg = <2 0x0 0x100>;
interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
phy-mode = "mii";
reg-io-width = <2>;
smsc,force-external-phy;
smsc,irq-push-pull;
/* SLOW chipselect config */
qcom,xmem-recovery-cycles = <0>;
qcom,xmem-write-hold-cycles = <3>;
qcom,xmem-write-delta-cycles = <31>;
qcom,xmem-read-delta-cycles = <28>;
qcom,xmem-write-wait-cycles = <9>;
qcom,xmem-read-wait-cycles = <9>;
};
};
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
View file @ 2a17bb8c
......@@ -126,8 +126,6 @@ required:
- compatible
- reg
- '#clock-cells'
- idt,shutdown
- idt,output-enable-active
allOf:
- if:
......
Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml deleted 100644 → 0
View file @ 19a519ca
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT6795
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The Mediatek system clock controller provides various clocks and system
configuration like reset and bus protection on MT6795.
properties:
compatible:
items:
- enum:
- mediatek,mt6795-apmixedsys
- mediatek,mt6795-infracfg
- mediatek,mt6795-pericfg
- mediatek,mt6795-topckgen
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
topckgen: clock-controller@10000000 {
compatible = "mediatek,mt6795-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
};
Documentation/devicetree/bindings/cpu/idle-states.yaml
View file @ 2a17bb8c
......@@ -385,7 +385,7 @@ patternProperties:
This property is required in idle state nodes of device tree meant
for RISC-V systems. For more details on the suspend_type parameter
refer the SBI specifiation v0.3 (or higher) [7].
refer the SBI specification v0.3 (or higher) [7].
local-timer-stop:
description:
......
Documentation/devicetree/bindings/display/fsl,lcdif.yaml
View file @ 2a17bb8c
......@@ -50,6 +50,14 @@ properties:
- const: disp_axi
minItems: 1
dmas:
items:
- description: DMA specifier for the RX DMA channel.
dma-names:
items:
- const: rx
interrupts:
items:
- description: LCDIF DMA interrupt
......@@ -156,6 +164,18 @@ allOf:
interrupts:
maxItems: 1
- if:
not:
properties:
compatible:
contains:
enum:
- fsl,imx28-lcdif
then:
properties:
dmas: false
dma-names: false
examples:
- |
#include <dt-bindings/clock/imx6sx-clock.h>
......
Documentation/devicetree/bindings/display/lvds.yaml
View file @ 2a17bb8c
......@@ -16,7 +16,7 @@ maintainers:
description:
This binding extends the data mapping defined in lvds-data-mapping.yaml.
It supports reversing the bit order on the formats defined there in order
to accomodate for even more specialized data formats, since a variety of
to accommodate for even more specialized data formats, since a variety of
data formats and layouts is used to drive LVDS displays.
properties:
......
Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml
View file @ 2a17bb8c
......@@ -84,11 +84,7 @@ properties:
- port@0
- port@1
backlight: true
enable-gpios: true
power-supply: true
additionalProperties: false
unevaluatedProperties: false
required:
- compatible
......
Documentation/devicetree/bindings/dma/nxp,lpc3220-dmamux.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/nxp,lpc3220-dmamux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DMA multiplexer for LPC32XX SoC (DMA request router)
maintainers:
- J.M.B. Downing <jonathan.downing@nautel.com>
- Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
allOf:
- $ref: dma-router.yaml#
properties:
compatible:
const: nxp,lpc3220-dmamux
reg:
maxItems: 1
dma-masters:
description: phandle to a dma node compatible with arm,pl080
maxItems: 1
"#dma-cells":
const: 3
description: |
First two cells same as for device pointed in dma-masters.
Third cell represents mux value for the request.
required:
- compatible
- reg
- dma-masters
additionalProperties: false
examples:
- |
dma-router@7c {
compatible = "nxp,lpc3220-dmamux";
reg = <0x7c 0x8>;
dma-masters = <&dma>;
#dma-cells = <3>;
};
...
Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt
View file @ 2a17bb8c
......@@ -20,7 +20,7 @@ Optional properties:
memcpy channels in eDMA.
Notes:
When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
When requesting channel via ti,dra7-dma-crossbar, the DMA client must request
the DMA event number as crossbar ID (input to the DMA crossbar).
For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
......
Documentation/devicetree/bindings/gnss/brcm,bcm4751.yaml
View file @ 2a17bb8c
......@@ -18,6 +18,7 @@ description:
allOf:
- $ref: gnss-common.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/gnss/gnss-common.yaml
View file @ 2a17bb8c
......@@ -35,11 +35,6 @@ properties:
GPIO line, this is used.
maxItems: 1
current-speed:
description: The baudrate in bits per second of the device as it comes
online, current active speed.
$ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: true
examples:
......
Documentation/devicetree/bindings/gnss/mediatek.yaml
View file @ 2a17bb8c
......@@ -15,6 +15,7 @@ description:
allOf:
- $ref: gnss-common.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/gnss/sirfstar.yaml
View file @ 2a17bb8c
......@@ -21,6 +21,7 @@ description:
allOf:
- $ref: gnss-common.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
View file @ 2a17bb8c
......@@ -8,6 +8,7 @@ title: U-blox GNSS Receiver
allOf:
- $ref: gnss-common.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
maintainers:
- Johan Hovold <johan@kernel.org>
......
Documentation/devicetree/bindings/iio/accel/lis302.txt
View file @ 2a17bb8c
......@@ -36,7 +36,7 @@ Optional properties for all bus drivers:
- st,irq{1,2}-disable: disable IRQ 1/2
- st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition
- st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition
- st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready contition
- st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready condition
- st,irq{1,2}-click: raise IRQ 1/2 on click condition
- st,irq-open-drain: consider IRQ lines open-drain
- st,irq-active-low: make IRQ lines active low
......
Documentation/devicetree/bindings/incomplete-devices.yaml
View file @ 2a17bb8c
......@@ -35,40 +35,184 @@ properties:
- description: Legacy compatibles used on Macintosh devices
enum:
- AAPL,3500
- AAPL,7500
- AAPL,8500
- AAPL,9500
- AAPL,accelerometer_1
- AAPL,e411
- AAPL,Gossamer
- AAPL,PowerBook1998
- AAPL,ShinerESB
- adm1030
- amd-0137
- B5221
- bmac+
- burgundy
- cobalt
- cy28508
- daca
- fcu
- gatwick
- gmac
- heathrow
- heathrow-ata
- heathrow-media-bay
- i2sbus
- i2s-modem
- iMac
- K2-GMAC
- k2-i2c
- K2-Keylargo
- K2-UATA
- kauai-ata
- Keylargo
- keylargo-ata
- keylargo-media-bay
- lm87cimt
- MAC,adm1030
- MAC,ds1775
- MacRISC
- MacRISC2
- MacRISC3
- MacRISC4
- max6690
- ohare
- ohare-media-bay
- ohare-swim3
- PowerBook1,1
- PowerBook2,1
- PowerBook2,2
- PowerBook3,1
- PowerBook3,2
- PowerBook3,3
- PowerBook3,4
- PowerBook3,5
- PowerBook4,1
- PowerBook4,2
- PowerBook4,3
- PowerBook5,1
- PowerBook5,2
- PowerBook5,3
- PowerBook5,4
- PowerBook5,5
- PowerBook5,6
- PowerBook5,7
- PowerBook5,8
- PowerBook5,9
- PowerBook6,3
- PowerBook6,5
- PowerBook6,7
- PowerMac10,1
- PowerMac10,2
- PowerMac1,1
- PowerMac11,2
- PowerMac12,1
- PowerMac2,1
- PowerMac2,2
- PowerMac3,1
- PowerMac3,4
- PowerMac3,5
- PowerMac3,6
- PowerMac4,1
- PowerMac4,2
- PowerMac4,4
- PowerMac4,5
- PowerMac7,2
- PowerMac7,3
- PowerMac8,1
- PowerMac8,2
- PowerMac9,1
- paddington
- RackMac1,1
- RackMac1,2
- RackMac3,1
- screamer
- shasta-ata
- sms
- smu-rpm-fans
- smu-sat
- smu-sensors
- snapper
- swim3
- tumbler
- u3-agp
- u3-dart
- u3-ht
- u4-dart
- u4-pcie
- U4-pcie
- uni-n-i2c
- uni-north
- description: Legacy compatibles used on other PowerPC devices
enum:
- 1682m-gizmo
- 1682m-gpio
- 1682m-rng
- 1682m-sdc
- amcc,ppc440epx-rng
- amcc,ppc460ex-bcsr
- amcc,ppc460ex-crypto
- amcc,ppc460ex-rng
- amcc,ppc460sx-crypto
- amcc,ppc4xx-crypto
- amcc,sata-460ex
- CBEA,platform-open-pic
- CBEA,platform-spider-pic
- direct-mapped
- display
- gpio-mdio
- hawk-bridge
- hawk-pci
- IBM,CBEA
- IBM,lhca
- IBM,lhea
- IBM,lhea-ethernet
- ibm,axon-msic
- Momentum,Apache
- Momentum,Maple
- mai-logic,articia-s
- mpc10x-pci
- mpc5200b-fec-phy
- mpc5200-serial
- mpc5200-sram
- nintendo,flipper
- nintendo,flipper-exi
- nintendo,flipper-pi
- nintendo,flipper-pic
- nintendo,hollywood
- nintendo,hollywood-pic
- nintendo,latte-exi
- nintendo,latte-srnprot
- ohci-be
- ohci-bigendian
- ohci-le
- PA6T-1682M
- pasemi,1682m-iob
- pasemi,localbus
- pasemi,localbus-nand
- pasemi,nemo
- pasemi,pwrficient
- pasemi,pwrficient-rng
- pasemi,rootbus
- pasemi,sdc
- soc
- sony,ps3
- sti,platform-spider-pic
- description: Legacy compatibles used on SPARC devices
enum:
- bq4802
- ds1287
- i2cpcf,8584
- isa-m5819p
- isa-m5823p
- m5819
- qcn
- sab82532
- su
- sun4v
- SUNW,bbc-beep
- SUNW,bbc-i2c
- SUNW,CS4231
......@@ -96,9 +240,13 @@ properties:
- compat1
- compat2
- compat3
- gpio-mockup
- gpio-simulator
- gpio-virtuser
- linux,spi-loopback-test
- mailbox-test
- regulator-virtual-consumer
- test-device
- description:
Devices on MIPS platform, without any DTS users. These are
......
Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.yaml
View file @ 2a17bb8c
......@@ -19,6 +19,7 @@ properties:
- qcom,pmi632-vib
- items:
- enum:
- qcom,pm6150-vib
- qcom,pm7250b-vib
- qcom,pm7325b-vib
- qcom,pm7550ba-vib
......
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
View file @ 2a17bb8c
......@@ -60,7 +60,7 @@ properties:
The 4th cell is a phandle to a node describing a set of CPUs this
interrupt is affine to. The interrupt must be a PPI, and the node
pointed must be a subnode of the "ppi-partitions" subnode. For
interrupt types other than PPI or PPIs that are not partitionned,
interrupt types other than PPI or PPIs that are not partitioned,
this cell must be zero. See the "ppi-partitions" node description
below.
......
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt deleted 100644 → 0
View file @ 19a519ca
Aspeed Vectored Interrupt Controller
These bindings are for the Aspeed interrupt controller. The AST2400 and
AST2500 SoC families include a legacy register layout before a re-designed
layout, but the bindings do not prescribe the use of one or the other.
Required properties:
- compatible : "aspeed,ast2400-vic"
"aspeed,ast2500-vic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
vic: interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1e6c0080 0x80>;
};
Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2400-vic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed Vectored Interrupt Controller
maintainers:
- Andrew Jeffery <andrew@codeconstruct.com.au>
description:
The AST2400 and AST2500 SoC families include a legacy register layout before
a redesigned layout, but the bindings do not prescribe the use of one or the
other.
properties:
compatible:
enum:
- aspeed,ast2400-vic
- aspeed,ast2500-vic
reg:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 1
description:
Specifies the number of cells needed to encode an interrupt source. It
must be 1 as the VIC has no configuration options for interrupt sources.
The single cell defines the interrupt number.
valid-sources:
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 2
description:
A bitmap of supported sources for the implementation.
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
allOf:
- $ref: /schemas/interrupt-controller.yaml
additionalProperties: false
examples:
- |
interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
reg = <0x1e6c0080 0x80>;
interrupt-controller;
#interrupt-cells = <1>;
valid-sources = <0xffffffff 0x0007ffff>;
};
...
Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
View file @ 2a17bb8c
......@@ -17,6 +17,7 @@ properties:
- enum:
- fsl,imx8m-irqsteer
- fsl,imx8mp-irqsteer
- fsl,imx8qm-irqsteer
- fsl,imx8qxp-irqsteer
- const: fsl,imx-irqsteer
......@@ -83,6 +84,7 @@ allOf:
contains:
enum:
- fsl,imx8mp-irqsteer
- fsl,imx8qm-irqsteer
- fsl,imx8qxp-irqsteer
then:
required:
......
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
View file @ 2a17bb8c
......@@ -27,6 +27,7 @@ properties:
items:
- enum:
- qcom,qdu1000-pdc
- qcom,sa8255p-pdc
- qcom,sa8775p-pdc
- qcom,sc7180-pdc
- qcom,sc7280-pdc
......
Documentation/devicetree/bindings/leds/awinic,aw200xx.yaml
View file @ 2a17bb8c
......@@ -66,7 +66,7 @@ patternProperties:
IMAXled = 160000 * (592 / 600.5) * (1 / max-current-switch-number)
And the minimum output current formula:
IMINled = 3300 * (592 / 600.5) * (1 / max-current-switch-number)
where max-current-switch-number is determinated by led configuration
where max-current-switch-number is determined by led configuration
and depends on how leds are physically connected to the led driver.
allOf:
......
Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt
View file @ 2a17bb8c
......@@ -24,7 +24,7 @@ Required properties:
number of completion messages for which FlexRM will inject
one MSI interrupt to CPU.
The 3nd cell contains MSI timer value representing time for
The 3rd cell contains MSI timer value representing time for
which FlexRM will wait to accumulate N completion messages
where N is the value specified by 2nd cell above. If FlexRM
does not get required number of completion messages in time
......
Documentation/devicetree/bindings/media/i2c/thine,thp7312.yaml
View file @ 2a17bb8c
......@@ -16,7 +16,7 @@ description:
can be connected to CMOS image sensors from various vendors, supporting both
MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
or parallel. The hardware is capable of transmitting and receiving MIPI
interlaved data strams with data types or multiple virtual channel
interleaved data streams with data types or multiple virtual channel
identifiers.
allOf:
......
Documentation/devicetree/bindings/media/samsung,exynos4210-fimc.yaml
View file @ 2a17bb8c
......@@ -77,7 +77,7 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 2
description: |
An array specyfing minimum image size in pixels at the FIMC input and
An array specifying minimum image size in pixels at the FIMC input and
output DMA, in the first and second cell respectively. Default value
is <16 16>.
......
Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml
View file @ 2a17bb8c
......@@ -25,7 +25,7 @@ properties:
description:
The PMIC provides intb and errb IRQ lines. The errb IRQ line is used
for fatal IRQs which will cause the PMIC to shut down power outputs.
In many systems this will shut down the SoC contolling the PMIC and
In many systems this will shut down the SoC controlling the PMIC and
connecting/handling the errb can be omitted. However, there are cases
where the SoC is not powered by the PMIC or has a short time backup
energy to handle shutdown of critical hardware. In that case it may be
......
Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml
View file @ 2a17bb8c
......@@ -53,7 +53,7 @@ properties:
samsung,s2mps11-wrstbi-ground:
description: |
Indicates that WRSTBI pin of PMIC is pulled down. When the system is
suspended it will always go down thus triggerring unwanted buck warm
suspended it will always go down thus triggering unwanted buck warm
reset (setting buck voltages to default values).
type: boolean
......
Documentation/devicetree/bindings/mfd/twl6040.txt
View file @ 2a17bb8c
......@@ -2,7 +2,7 @@ Texas Instruments TWL6040 family
The TWL6040s are 8-channel high quality low-power audio codecs providing audio,
vibra and GPO functionality on OMAP4+ platforms.
They are connected ot the host processor via i2c for commands, McPDM for audio
They are connected to the host processor via i2c for commands, McPDM for audio
data and commands.
Required properties:
......
Documentation/devicetree/bindings/misc/aspeed,ast2400-cvic.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/aspeed,ast2400-cvic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed Coprocessor Vectored Interrupt Controller
maintainers:
- Andrew Jeffery <andrew@codeconstruct.com.au>
description:
The Aspeed AST2400 and AST2500 SoCs have a controller that provides interrupts
to the ColdFire coprocessor. It's not a normal interrupt controller and it
would be rather inconvenient to create an interrupt tree for it, as it
somewhat shares some of the same sources as the main ARM interrupt controller
but with different numbers.
The AST2500 also supports a software generated interrupt.
properties:
compatible:
items:
- enum:
- aspeed,ast2400-cvic
- aspeed,ast2500-cvic
- const: aspeed,cvic
reg:
maxItems: 1
valid-sources:
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description:
A bitmap of supported sources for the implementation.
copro-sw-interrupts:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
A list of interrupt numbers that can be used as software interrupts from
the ARM to the coprocessor.
required:
- compatible
- reg
- valid-sources
additionalProperties: false
examples:
- |
interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2500-cvic", "aspeed,cvic";
reg = <0x1e6c2000 0x80>;
valid-sources = <0xffffffff>;
copro-sw-interrupts = <1>;
};
Documentation/devicetree/bindings/misc/aspeed,cvic.txt deleted 100644 → 0
View file @ 19a519ca
* ASPEED AST2400 and AST2500 coprocessor interrupt controller
This file describes the bindings for the interrupt controller present
in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
ColdFire coprocessor.
It is not a normal interrupt controller and it would be rather
inconvenient to create an interrupt tree for it as it somewhat shares
some of the same sources as the main ARM interrupt controller but with
different numbers.
The AST2500 supports a SW generated interrupt
Required properties:
- reg: address and length of the register for the device.
- compatible: "aspeed,cvic" and one of:
"aspeed,ast2400-cvic"
or
"aspeed,ast2500-cvic"
- valid-sources: One cell, bitmap of supported sources for the implementation
Optional properties;
- copro-sw-interrupts: List of interrupt numbers that can be used as
SW interrupts from the ARM to the coprocessor.
(AST2500 only)
Example:
cvic: copro-interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2500-cvic";
valid-sources = <0xffffffff>;
copro-sw-interrupts = <1>;
reg = <0x1e6c2000 0x80>;
};
Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml → Documentation/devicetree/bindings/net/bluetooth/brcm,bluetooth.yaml
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/broadcom-bluetooth.yaml#
$id: http://devicetree.org/schemas/net/bluetooth/brcm,bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Bluetooth Chips
......@@ -119,29 +119,28 @@ properties:
items:
- const: host-wakeup
max-speed: true
current-speed: true
required:
- compatible
dependencies:
brcm,requires-autobaud-mode: [ shutdown-gpios ]
if:
not:
properties:
compatible:
contains:
enum:
- brcm,bcm20702a1
- brcm,bcm4329-bt
- brcm,bcm4330-bt
then:
properties:
reset-gpios: false
additionalProperties: false
allOf:
- $ref: /schemas/serial/serial-peripheral-props.yaml#
- if:
not:
properties:
compatible:
contains:
enum:
- brcm,bcm20702a1
- brcm,bcm4329-bt
- brcm,bcm4330-bt
then:
properties:
reset-gpios: false
unevaluatedProperties: false
examples:
- |
......
Documentation/devicetree/bindings/net/marvell-bluetooth.yaml → Documentation/devicetree/bindings/net/bluetooth/marvell,88w8897.yaml
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/marvell-bluetooth.yaml#
$id: http://devicetree.org/schemas/net/bluetooth/marvell,88w8897.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Bluetooth chips
......@@ -19,13 +19,13 @@ properties:
- mrvl,88w8897
- mrvl,88w8997
max-speed:
description: see Documentation/devicetree/bindings/serial/serial.yaml
max-speed: true
required:
- compatible
allOf:
- $ref: /schemas/serial/serial-peripheral-props.yaml#
- if:
properties:
compatible:
......
Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml
View file @ 2a17bb8c
......@@ -72,7 +72,7 @@ properties:
description: VDD_RFA_CMN supply regulator handle
vddrfa0p8-supply:
description: VDD_RFA_0P8 suppply regulator handle
description: VDD_RFA_0P8 supply regulator handle
vddrfa1p7-supply:
description: VDD_RFA_1P7 supply regulator handle
......@@ -98,8 +98,7 @@ properties:
vddwlmx-supply:
description: VDD_WLMX supply regulator handle
max-speed:
description: see Documentation/devicetree/bindings/serial/serial.yaml
max-speed: true
firmware-name:
description: specify the name of nvm firmware to load
......@@ -118,6 +117,7 @@ additionalProperties: false
allOf:
- $ref: bluetooth-controller.yaml#
- $ref: /schemas/serial/serial-peripheral-props.yaml#
- if:
properties:
compatible:
......
Documentation/devicetree/bindings/net/realtek-bluetooth.yaml → Documentation/devicetree/bindings/net/bluetooth/realtek,bluetooth.yaml
View file @ 2a17bb8c
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/realtek-bluetooth.yaml#
$id: http://devicetree.org/schemas/net/bluetooth/realtek,bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RTL8723BS/RTL8723CS/RTL8821CS/RTL8822CS Bluetooth
......@@ -46,6 +46,9 @@ properties:
required:
- compatible
allOf:
- $ref: /schemas/serial/serial-peripheral-props.yaml#
additionalProperties: false
examples:
......
Documentation/devicetree/bindings/net/ti,bluetooth.yaml → Documentation/devicetree/bindings/net/bluetooth/ti,bluetooth.yaml
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,bluetooth.yaml#
$id: http://devicetree.org/schemas/net/bluetooth/ti,bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments Bluetooth Chips
......@@ -74,6 +74,9 @@ properties:
required:
- compatible
allOf:
- $ref: /schemas/serial/serial-peripheral-props.yaml#
additionalProperties: false
examples:
......
Documentation/devicetree/bindings/net/fsl,cpm-enet.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/fsl,cpm-enet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Network for cpm enet
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,cpm1-scc-enet
- fsl,cpm2-scc-enet
- fsl,cpm1-fec-enet
- fsl,cpm2-fcc-enet
- fsl,qe-enet
- items:
- enum:
- fsl,mpc8272-fcc-enet
- const: fsl,cpm2-fcc-enet
reg:
minItems: 1
maxItems: 3
interrupts:
maxItems: 1
fsl,cpm-command:
$ref: /schemas/types.yaml#/definitions/uint32
description: cpm command
required:
- compatible
- reg
- interrupts
allOf:
- $ref: ethernet-controller.yaml
unevaluatedProperties: false
examples:
- |
ethernet@11300 {
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <0x11300 0x20 0x8400 0x100 0x11390 1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <20 8>;
interrupt-parent = <&pic>;
phy-handle = <&phy0>;
fsl,cpm-command = <0x12000300>;
};
Documentation/devicetree/bindings/net/fsl,cpm-mdio.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale CPM MDIO Device
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,pq1-fec-mdio
- fsl,cpm2-mdio-bitbang
- items:
- const: fsl,mpc8272ads-mdio-bitbang
- const: fsl,mpc8272-mdio-bitbang
- const: fsl,cpm2-mdio-bitbang
reg:
maxItems: 1
fsl,mdio-pin:
$ref: /schemas/types.yaml#/definitions/uint32
description: pin of port C controlling mdio data
fsl,mdc-pin:
$ref: /schemas/types.yaml#/definitions/uint32
description: pin of port C controlling mdio clock
required:
- compatible
- reg
allOf:
- $ref: mdio.yaml#
unevaluatedProperties: false
examples:
- |
mdio@10d40 {
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
reg = <0x10d40 0x14>;
#address-cells = <1>;
#size-cells = <0>;
fsl,mdio-pin = <12>;
fsl,mdc-pin = <13>;
};
Documentation/devicetree/bindings/net/maxim,ds26522.txt deleted 100644 → 0
View file @ 19a519ca
* Maxim (Dallas) DS26522 Dual T1/E1/J1 Transceiver
Required properties:
- compatible: Should contain "maxim,ds26522".
- reg: SPI CS.
- spi-max-frequency: SPI clock.
Example:
slic@1 {
compatible = "maxim,ds26522";
reg = <1>;
spi-max-frequency = <2000000>; /* input clock */
};
Documentation/devicetree/bindings/net/maxim,ds26522.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/maxim,ds26522.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim (Dallas) DS26522 Dual T1/E1/J1 Transceiver
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
items:
- const: maxim,ds26522
reg:
maxItems: 1
required:
- compatible
- reg
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
transceiver@1 {
compatible = "maxim,ds26522";
reg = <1>;
spi-max-frequency = <2000000>; /* input clock */
};
};
Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
View file @ 2a17bb8c
......@@ -36,7 +36,7 @@ Optional properties:
3-tuple setting for each (up to 3) supported link
speed on the host. Range is 0 to 273000 in unit of
uV. Default is 0.
- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of
- apm,tx-pre-cursor2 : 2nd pre-cursor emphasis taps control. Two set of
3-tuple setting for each (up to 3) supported link
speed on the host. Range is 0 to 127400 in unit uV.
Default is 0x0.
......
Documentation/devicetree/bindings/phy/mediatek,mt7988-xfi-tphy.yaml
View file @ 2a17bb8c
......@@ -41,7 +41,7 @@ properties:
description:
One instance of the T-PHY on MT7988 suffers from a performance
problem in 10GBase-R mode which needs a work-around in the driver.
This flag enables a work-around ajusting an analog phy setting and
This flag enables a work-around adjusting an analog phy setting and
is required for XFI Port0 of the MT7988 SoC to be in compliance with
the SFP specification.
......
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
View file @ 2a17bb8c
......@@ -240,7 +240,7 @@ patternProperties:
The force mode is used to manually switch the shared phy mode between
USB3 and PCIe, when USB3 phy type is selected by the consumer, and
force-mode is set, will cause phy's power and pipe toggled and force
phy as USB3 mode which switched from default PCIe mode. But perfer to
phy as USB3 mode which switched from default PCIe mode. But prefer to
use the property "mediatek,syscon-type" for newer SoCs that support it.
type: boolean
......
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml
View file @ 2a17bb8c
......@@ -43,7 +43,7 @@ properties:
qcom,tune-usb2-amplitude:
$ref: /schemas/types.yaml#/definitions/uint8
description: High-Speed trasmit amplitude
description: High-Speed transmit amplitude
minimum: 0
maximum: 15
default: 8
......
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View file @ 2a17bb8c
......@@ -11,7 +11,7 @@ maintainers:
- Alexandre TORGUE <alexandre.torgue@foss.st.com>
description: |
STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
STMicroelectronics's STM32 MCUs integrate a GPIO and Pin mux/config hardware
controller. It controls the input/output settings on the available pins and
also provides ability to multiplex and configure the output of various
on-chip controllers onto these pads.
......@@ -164,7 +164,7 @@ patternProperties:
This macro is available here:
- include/dt-bindings/pinctrl/stm32-pinfunc.h
Some examples of using macro:
/* GPIO A9 set as alernate function 2 */
/* GPIO A9 set as alternate function 2 */
... {
pinmux = <STM32_PINMUX('A', 9, AF2)>;
};
......
Documentation/devicetree/bindings/power/wakeup-source.txt
View file @ 2a17bb8c
......@@ -26,7 +26,7 @@ List of legacy properties and respective binding document
3. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
Documentation/devicetree/bindings/mfd/tc3589x.txt
Documentation/devicetree/bindings/input/touchscreen/ads7846.txt
4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8921-keypad.yaml
5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung,s3c6410-keypad.yaml
6. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
......
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml
View file @ 2a17bb8c
......@@ -93,7 +93,7 @@ patternProperties:
Each SCP core has own cache memory. The SRAM and L1TCM are shared by
cores. The power of cache, SRAM and L1TCM power should be enabled
before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
on differnt SoCs.
on different SoCs.
The SCP cores do not use an MMU, but has a set of registers to
control the translations between 32-bit CPU addresses into system bus
......
Documentation/devicetree/bindings/rtc/fsl,ls-ftm-alarm.yaml
View file @ 2a17bb8c
......@@ -42,7 +42,7 @@ properties:
minItems: 1
description:
phandle to rcpm node, Please refer
Documentation/devicetree/bindings/soc/fsl/rcpm.txt
Documentation/devicetree/bindings/soc/fsl/fsl,rcpm.yaml
big-endian:
$ref: /schemas/types.yaml#/definitions/flag
......
Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml
View file @ 2a17bb8c
......@@ -78,7 +78,7 @@ properties:
we use nvidia,adjust-baud-rates.
As an example, consider there is deviation observed in TX for baud rates as listed below. 0
to 9600 has 1% deviation 9600 to 115200 2% deviation. This slight deviation is expcted and
to 9600 has 1% deviation 9600 to 115200 2% deviation. This slight deviation is expected and
Tegra UART is expected to handle it. Due to the issue stated above, baud rate on Tegra UART
should be set equal to or above deviation observed for avoiding frame errors. Property
should be set like this:
......
Documentation/devicetree/bindings/serial/serial-peripheral-props.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/serial-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Serial-attached Devices
maintainers:
- Rob Herring <robh@kernel.org>
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
description:
Devices connected over serial/UART, expressed as children of a serial
controller, might need similar properties, e.g. for configuring the baud
rate.
properties:
max-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The maximum baud rate the device operates at.
This should only be present if the maximum is less than the slave
device can support. For example, a particular board has some
signal quality issue or the host processor can't support higher
baud rates.
current-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The current baud rate the device operates at.
This should only be present in case a driver has no chance to know
the baud rate of the slave device.
Examples:
* device supports auto-baud
* the rate is setup by a bootloader and there is no way to reset
the device
* device baud rate is configured by its firmware but there is no
way to request the actual settings
additionalProperties: true
Documentation/devicetree/bindings/serial/serial.yaml
View file @ 2a17bb8c
......@@ -92,6 +92,8 @@ patternProperties:
if:
type: object
then:
additionalProperties: true
$ref: serial-peripheral-props.yaml#
description:
Serial attached devices shall be a child node of the host UART device
the slave device is attached to. It is expected that the attached
......@@ -103,28 +105,6 @@ patternProperties:
description:
Compatible of the device connected to the serial port.
max-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The maximum baud rate the device operates at.
This should only be present if the maximum is less than the slave
device can support. For example, a particular board has some
signal quality issue or the host processor can't support higher
baud rates.
current-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The current baud rate the device operates at.
This should only be present in case a driver has no chance to know
the baud rate of the slave device.
Examples:
* device supports auto-baud
* the rate is setup by a bootloader and there is no way to reset
the device
* device baud rate is configured by its firmware but there is no
way to request the actual settings
required:
- compatible
......
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: High-Level Data Link Control(HDLC)
description: HDLC part in Universal communication controllers (UCCs)
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,ucc-hdlc
reg:
maxItems: 1
interrupts:
maxItems: 1
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
rx-clock-name:
$ref: /schemas/types.yaml#/definitions/string
oneOf:
- pattern: "^brg([0-9]|1[0-6])$"
- pattern: "^clk([0-9]|1[0-9]|2[0-4])$"
tx-clock-name:
$ref: /schemas/types.yaml#/definitions/string
oneOf:
- pattern: "^brg([0-9]|1[0-6])$"
- pattern: "^clk([0-9]|1[0-9]|2[0-4])$"
fsl,tdm-interface:
$ref: /schemas/types.yaml#/definitions/flag
description: Specify that hdlc is based on tdm-interface
fsl,rx-sync-clock:
$ref: /schemas/types.yaml#/definitions/string
description: rx-sync
enum:
- none
- rsync_pin
- brg9
- brg10
- brg11
- brg13
- brg14
- brg15
fsl,tx-sync-clock:
$ref: /schemas/types.yaml#/definitions/string
description: tx-sync
enum:
- none
- tsync_pin
- brg9
- brg10
- brg11
- brg13
- brg14
- brg15
fsl,tdm-framer-type:
$ref: /schemas/types.yaml#/definitions/string
description: required for tdm interface
enum: [e1, t1]
fsl,tdm-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: number of TDM ID
fsl,tx-timeslot-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description:
required for tdm interface.
time slot mask for TDM operation. Indicates which time
slots used for transmitting and receiving.
fsl,rx-timeslot-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description:
required for tdm interface.
time slot mask for TDM operation. Indicates which time
slots used for transmitting and receiving.
fsl,siram-entry-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
required for tdm interface
Must be 0,2,4...64. the number of TDM entry.
fsl,tdm-internal-loopback:
$ref: /schemas/types.yaml#/definitions/flag
description:
optional for tdm interface
Internal loopback connecting on TDM layer.
fsl,hmask:
$ref: /schemas/types.yaml#/definitions/uint16
description: |
HDLC address recognition. Set to zero to disable
address filtering of packets:
fsl,hmask = /bits/ 16 <0x0000>;
required:
- compatible
- reg
additionalProperties: false
examples:
- |
communication@2000 {
compatible = "fsl,ucc-hdlc";
reg = <0x2000 0x200>;
rx-clock-name = "clk8";
tx-clock-name = "clk9";
fsl,rx-sync-clock = "rsync_pin";
fsl,tx-sync-clock = "tsync_pin";
fsl,tx-timeslot-mask = <0xfffffffe>;
fsl,rx-timeslot-mask = <0xfffffffe>;
fsl,tdm-framer-type = "e1";
fsl,tdm-id = <0>;
fsl,siram-entry-id = <0>;
fsl,tdm-interface;
};
- |
communication@2000 {
compatible = "fsl,ucc-hdlc";
reg = <0x2000 0x200>;
rx-clock-name = "brg1";
tx-clock-name = "brg1";
};
Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt deleted 100644 → 0
View file @ 19a519ca
* Network
Currently defined compatibles:
- fsl,cpm1-scc-enet
- fsl,cpm2-scc-enet
- fsl,cpm1-fec-enet
- fsl,cpm2-fcc-enet (third resource is GFEMR)
- fsl,qe-enet
Example:
ethernet@11300 {
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11300 20 8400 100 11390 1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <20 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
fsl,cpm-command = <12000300>;
};
* MDIO
Currently defined compatibles:
fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
fsl,cpm2-mdio-bitbang (reg is port C registers)
Properties for fsl,cpm2-mdio-bitbang:
fsl,mdio-pin : pin of port C controlling mdio data
fsl,mdc-pin : pin of port C controlling mdio clock
Example:
mdio@10d40 {
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
reg = <10d40 14>;
#address-cells = <1>;
#size-cells = <0>;
fsl,mdio-pin = <12>;
fsl,mdc-pin = <13>;
};
* HDLC
Currently defined compatibles:
- fsl,ucc-hdlc
Properties for fsl,ucc-hdlc:
- rx-clock-name
- tx-clock-name
Usage: required
Value type: <string>
Definition : Must be "brg1"-"brg16" for internal clock source,
Must be "clk1"-"clk24" for external clock source.
- fsl,tdm-interface
Usage: optional
Value type: <empty>
Definition : Specify that hdlc is based on tdm-interface
The property below is dependent on fsl,tdm-interface:
- fsl,rx-sync-clock
Usage: required
Value type: <string>
Definition : Must be "none", "rsync_pin", "brg9-11" and "brg13-15".
- fsl,tx-sync-clock
Usage: required
Value type: <string>
Definition : Must be "none", "tsync_pin", "brg9-11" and "brg13-15".
- fsl,tdm-framer-type
Usage: required for tdm interface
Value type: <string>
Definition : "e1" or "t1".Now e1 and t1 are used, other framer types
are not supported.
- fsl,tdm-id
Usage: required for tdm interface
Value type: <u32>
Definition : number of TDM ID
- fsl,tx-timeslot-mask
- fsl,rx-timeslot-mask
Usage: required for tdm interface
Value type: <u32>
Definition : time slot mask for TDM operation. Indicates which time
slots used for transmitting and receiving.
- fsl,siram-entry-id
Usage: required for tdm interface
Value type: <u32>
Definition : Must be 0,2,4...64. the number of TDM entry.
- fsl,tdm-internal-loopback
usage: optional for tdm interface
value type: <empty>
Definition : Internal loopback connecting on TDM layer.
- fsl,hmask
usage: optional
Value type: <u16>
Definition: HDLC address recognition. Set to zero to disable
address filtering of packets:
fsl,hmask = /bits/ 16 <0x0000>;
Example for tdm interface:
ucc@2000 {
compatible = "fsl,ucc-hdlc";
rx-clock-name = "clk8";
tx-clock-name = "clk9";
fsl,rx-sync-clock = "rsync_pin";
fsl,tx-sync-clock = "tsync_pin";
fsl,tx-timeslot-mask = <0xfffffffe>;
fsl,rx-timeslot-mask = <0xfffffffe>;
fsl,tdm-framer-type = "e1";
fsl,tdm-id = <0>;
fsl,siram-entry-id = <0>;
fsl,tdm-interface;
};
Example for hdlc without tdm interface:
ucc@2000 {
compatible = "fsl,ucc-hdlc";
rx-clock-name = "brg1";
tx-clock-name = "brg1";
};
Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml
View file @ 2a17bb8c
......@@ -23,6 +23,9 @@ properties:
- fsl,ls1028a-scfg
- fsl,ls1043a-scfg
- fsl,ls1046a-scfg
- fsl,ls1088a-isc
- fsl,ls2080a-isc
- fsl,lx2160a-isc
- const: syscon
reg:
......
Documentation/devicetree/bindings/soc/fsl/fsl,rcpm.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/fsl,rcpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Run Control and Power Management
description:
The RCPM performs all device-level tasks associated with device run control
and power management.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,p2041-rcpm
- fsl,p3041-rcpm
- fsl,p4080-rcpm
- fsl,p5020-rcpm
- fsl,p5040-rcpm
- const: fsl,qoriq-rcpm-1.0
- items:
- enum:
- fsl,b4420-rcpm
- fsl,b4860-rcpm
- fsl,t4240-rcpm
- const: fsl,qoriq-rcpm-2.0
- items:
- enum:
- fsl,t1040-rcpm
- const: fsl,qoriq-rcpm-2.1
- items:
- enum:
- fsl,ls1012a-rcpm
- fsl,ls1021a-rcpm
- fsl,ls1028a-rcpm
- fsl,ls1043a-rcpm
- fsl,ls1046a-rcpm
- fsl,ls1088a-rcpm
- fsl,ls208xa-rcpm
- fsl,lx2160a-rcpm
- const: fsl,qoriq-rcpm-2.1+
reg:
maxItems: 1
"#fsl,rcpm-wakeup-cells":
description: |
The number of IPPDEXPCR register cells in the
fsl,rcpm-wakeup property.
Freescale RCPM Wakeup Source Device Tree Bindings
Required fsl,rcpm-wakeup property should be added to a device node if
the device can be used as a wakeup source.
fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
register cells. The number of IPPDEXPCR register cells is defined in
"#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is
the bit mask that should be set in IPPDEXPCR0, and the second register
cell is for IPPDEXPCR1, and so on.
Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
mechanism for keeping certain blocks awake during STANDBY and MEM, in
order to use them as wake-up sources.
little-endian:
$ref: /schemas/types.yaml#/definitions/flag
description:
RCPM register block is Little Endian. Without it RCPM
will be Big Endian (default case).
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
global-utilities@e2000 {
compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
reg = <0xe2000 0x1000>;
#fsl,rcpm-wakeup-cells = <2>;
};
Documentation/devicetree/bindings/soc/fsl/rcpm.txt deleted 100644 → 0
View file @ 19a519ca
* Run Control and Power Management
-------------------------------------------
The RCPM performs all device-level tasks associated with device run control
and power management.
Required properites:
- reg : Offset and length of the register set of the RCPM block.
- #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
fsl,rcpm-wakeup property.
- compatible : Must contain a chip-specific RCPM block compatible string
and (if applicable) may contain a chassis-version RCPM compatible
string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
such as:
* "fsl,p2041-rcpm"
* "fsl,p5020-rcpm"
* "fsl,t4240-rcpm"
Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
such as:
* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
* "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------------------------
1.0 p4080, p5020, p5040, p2041, p3041
2.0 t4240, b4860, b4420
2.1 t1040,
2.1+ ls1021a, ls1012a, ls1043a, ls1046a
Optional properties:
- little-endian : RCPM register block is Little Endian. Without it RCPM
will be Big Endian (default case).
Example:
The RCPM node for T4240:
rcpm: global-utilities@e2000 {
compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
reg = <0xe2000 0x1000>;
#fsl,rcpm-wakeup-cells = <2>;
};
* Freescale RCPM Wakeup Source Device Tree Bindings
-------------------------------------------
Required fsl,rcpm-wakeup property should be added to a device node if the device
can be used as a wakeup source.
- fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
register cells. The number of IPPDEXPCR register cells is defined in
"#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is
the bit mask that should be set in IPPDEXPCR0, and the second register
cell is for IPPDEXPCR1, and so on.
Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
mechanism for keeping certain blocks awake during STANDBY and MEM, in
order to use them as wake-up sources.
Example:
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clock-names = "ipg";
fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>;
};
Documentation/devicetree/bindings/sound/everest,es8326.yaml
View file @ 2a17bb8c
......@@ -32,7 +32,7 @@ properties:
description: |
just the value of reg 57. Bit(3) decides whether the jack polarity is inverted.
Bit(2) decides whether the button on the headset is inverted.
Bit(1)/(0) decides the mic properity to be OMTP/CTIA or auto.
Bit(1)/(0) decides the mic property to be OMTP/CTIA or auto.
minimum: 0x00
maximum: 0x0f
default: 0x0f
......
Documentation/devicetree/bindings/sound/serial-midi.yaml
View file @ 2a17bb8c
......@@ -22,6 +22,9 @@ description:
configure the clocks of the parent serial device so that a requested baud of 38.4 kBaud
results in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default)
allOf:
- $ref: /schemas/serial/serial-peripheral-props.yaml#
properties:
compatible:
const: serial-midi
......
Documentation/devicetree/bindings/sound/st,sta350.txt
View file @ 2a17bb8c
......@@ -77,7 +77,7 @@ Optional properties:
- st,odd-pwm-speed-mode:
If present, PWM speed mode run on odd speed mode (341.3 kHz) on all
channels. If not present, normal PWM spped mode (384 kHz) will be used.
channels. If not present, normal PWM speed mode (384 kHz) will be used.
- st,distortion-compensation:
If present, distortion compensation variable uses DCC coefficient.
......
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View file @ 2a17bb8c
......@@ -311,7 +311,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 1 (new calbiration data: for pre v1 IP):
// Example 1 (new calibration data: for pre v1 IP):
thermal-sensor@4a9000 {
compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
reg = <0x4a9000 0x1000>, /* TM */
......
Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt deleted 100644 → 0
View file @ 19a519ca
Freescale FlexTimer Module (FTM) Timer
Required properties:
- compatible : should be "fsl,ftm-timer"
- reg : Specifies base physical address and size of the register sets for the
clock event device and clock source device.
- interrupts : Should be the clock event device interrupt.
- clocks : The clocks provided by the SoC to drive the timer, must contain an
entry for each entry in clock-names.
- clock-names : Must include the following entries:
o "ftm-evt"
o "ftm-src"
o "ftm-evt-counter-en"
o "ftm-src-counter-en"
- big-endian: One boolean property, the big endian mode will be in use if it is
present, or the little endian mode will be in use for all the device registers.
Example:
ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm-evt", "ftm-src",
"ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>,
<&clks VF610_CLK_FTM3>,
<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
big-endian;
};
Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/fsl,ftm-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale FlexTimer Module (FTM) Timer
maintainers:
- Animesh Agarwal <animeshagarwal28@gmail.com>
properties:
compatible:
const: fsl,ftm-timer
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
description: The clocks provided by the SoC to drive the timer, must
contain an entry for each entry in clock-names.
minItems: 4
maxItems: 4
clock-names:
items:
- const: ftm-evt
- const: ftm-src
- const: ftm-evt-counter-en
- const: ftm-src-counter-en
big-endian: true
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ftm-evt", "ftm-src", "ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>, <&clks VF610_CLK_FTM3>,
<&clks VF610_CLK_FTM2_EXT_FIX_EN>, <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
big-endian;
};
Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.txt deleted 100644 → 0
View file @ 19a519ca
* NXP LPC3220 timer
The NXP LPC3220 timer is used on a wide range of NXP SoCs. This
includes LPC32xx, LPC178x, LPC18xx and LPC43xx parts.
Required properties:
- compatible:
Should be "nxp,lpc3220-timer".
- reg:
Address and length of the register set.
- interrupts:
Reference to the timer interrupt
- clocks:
Should contain a reference to timer clock.
- clock-names:
Should contain "timerclk".
Example:
timer1: timer@40085000 {
compatible = "nxp,lpc3220-timer";
reg = <0x40085000 0x1000>;
interrupts = <13>;
clocks = <&ccu1 CLK_CPU_TIMER1>;
clock-names = "timerclk";
};
Documentation/devicetree/bindings/timer/nxp,lpc3220-timer.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/nxp,lpc3220-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC3220 timer
maintainers:
- Animesh Agarwal <animeshagarwal28@gmail.com>
description: |
The NXP LPC3220 timer is used on a wide range of NXP SoCs. This includes
LPC32xx, LPC178x, LPC18xx and LPC43xx parts.
properties:
compatible:
const: nxp,lpc3220-timer
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: timerclk
resets:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/lpc32xx-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
timer@4004c000 {
compatible = "nxp,lpc3220-timer";
reg = <0x4004c000 0x1000>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk LPC32XX_CLK_TIMER1>;
clock-names = "timerclk";
};
Documentation/devicetree/bindings/timer/ti,da830-timer.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/ti,da830-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DaVinci Timer
maintainers:
- Kousik Sanagavarapu <five231003@gmail.com>
description: |
This is a 64-bit timer found on TI's DaVinci architecture devices. The timer
can be configured as a general-purpose 64-bit timer, dual general-purpose
32-bit timers. When configured as dual 32-bit timers, each half can operate
in conjunction (chain mode) or independently (unchained mode) of each other.
The timer is a free running up-counter and can generate interrupts when the
counter reaches preset counter values.
properties:
compatible:
const: ti,da830-timer
reg:
maxItems: 1
interrupts:
minItems: 2
maxItems: 10
interrupt-names:
minItems: 2
items:
- const: tint12
- const: tint34
- const: cmpint0
- const: cmpint1
- const: cmpint2
- const: cmpint3
- const: cmpint4
- const: cmpint5
- const: cmpint6
- const: cmpint7
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
additionalProperties: false
examples:
- |
timer@20000 {
compatible = "ti,da830-timer";
reg = <0x20000 0x1000>;
interrupts = <21>, <22>;
interrupt-names = "tint12", "tint34";
clocks = <&pll0_auxclk>;
};
...
Documentation/devicetree/bindings/timer/ti,davinci-timer.txt deleted 100644 → 0
View file @ 19a519ca
* Device tree bindings for Texas Instruments DaVinci timer
This document provides bindings for the 64-bit timer in the DaVinci
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.
The timer is a free running up-counter and can generate interrupts when the
counter reaches preset counter values.
Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
watchdog timers.
Required properties:
- compatible : should be "ti,da830-timer".
- reg : specifies base physical address and count of the registers.
- interrupts : interrupts generated by the timer.
- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
"cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6",
"cmpint7" ("cmpintX" may be omitted if not present in the
hardware).
- clocks : the clock feeding the timer clock.
Example:
clocksource: timer@20000 {
compatible = "ti,da830-timer";
reg = <0x20000 0x1000>;
interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>,
<80>, <81>;
interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1",
"cmpint2", "cmpint3", "cmpint4", "cmpint5",
"cmpint6", "cmpint7";
clocks = <&pll0_auxclk>;
};
Documentation/devicetree/bindings/trivial-devices.yaml
View file @ 2a17bb8c
......@@ -33,7 +33,8 @@ properties:
# Acbel fsg032 power supply
- acbel,fsg032
# SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
- ad,ad7414
- ad,ad7414 # Deprecated, use adi,ad7414
- adi,ad7414
# ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
- ad,adm9240
# AD5110 - Nonvolatile Digital Potentiometer
......@@ -46,8 +47,6 @@ properties:
- ams,iaq-core
# Temperature monitoring of Astera Labs PT5161L PCIe retimer
- asteralabs,pt5161l
# i2c serial eeprom (24cxx)
- at,24c08
# i2c h/w elliptic curve crypto module
- atmel,atecc508a
# ATSHA204 - i2c h/w symmetric crypto module
......@@ -70,14 +69,10 @@ properties:
- dallas,ds1631
# Total-Elapsed-Time Recorder with Alarm
- dallas,ds1682
# Tiny Digital Thermometer and Thermostat
- dallas,ds1775
# CPU Peripheral Monitor
- dallas,ds1780
# CPU Supervisor with Nonvolatile Memory and Programmable I/O
- dallas,ds4510
# Digital Thermometer and Thermostat
- dallas,ds75
# Delta AHE-50DC Open19 power shelf fan control module
- delta,ahe50dc-fan
# Delta Electronics DPS-650-AB power supply
......@@ -162,6 +157,8 @@ properties:
- isil,isl29030
# Intersil ISL68137 Digital Output Configurable PWM Controller
- isil,isl68137
# Intersil ISL69260 PMBus Voltage Regulator
- isil,isl69260
# Intersil ISL69269 PMBus Voltage Regulator
- isil,isl69269
# Intersil ISL76682 Ambient Light Sensor
......@@ -180,8 +177,6 @@ properties:
- maxim,ds1803-100
# 10 kOhm digital potentiometer with I2C interface
- maxim,ds3502
# Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
- maxim,max1237
# Temperature Sensor, I2C interface
- maxim,max1619
# 3-Channel Remote Temperature Sensor
......@@ -196,8 +191,6 @@ properties:
- maxim,max5484
# PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
- maxim,max6621
# 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
- maxim,max6625
# mCube 3-axis 8-bit digital accelerometer
- mcube,mc3230
# Measurement Specialities I2C temperature and humidity sensor
......@@ -362,8 +355,6 @@ properties:
- skyworks,sky81452
# SparkFun Qwiic Joystick (COM-15168) with i2c interface
- sparkfun,qwiic-joystick
# i2c serial eeprom (24cxx)
- st,24c256
# Sierra Wireless mangOH Green SPI IoT interface
- swir,mangoh-iotport-spi
# Ambient Light Sensor with SMBUS/Two Wire Serial Interface
......@@ -395,8 +386,6 @@ properties:
- ti,tmp121
- ti,tmp122
- ti,tmp125
# Digital Temperature Sensor
- ti,tmp275
# TI DC-DC converter on PMBus
- ti,tps40400
# TI Dual channel DCAP+ multiphase controller TPS53676 with AVSBus
......@@ -410,6 +399,7 @@ properties:
- ti,tps544b25
- ti,tps544c20
- ti,tps544c25
- ti,tps546d24
# I2C Touch-Screen Controller
- ti,tsc2003
# Vicor Corporation Digital Supervisor
......
Documentation/devicetree/bindings/watchdog/davinci-wdt.txt deleted 100644 → 0
View file @ 19a519ca
Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
Required properties:
- compatible : Should be "ti,davinci-wdt", "ti,keystone-wdt"
- reg : Should contain WDT registers location and length
Optional properties:
- timeout-sec : Contains the watchdog timeout in seconds
- clocks : the clock feeding the watchdog timer.
Needed if platform uses clocks.
See clock-bindings.txt
Documentation:
Davinci DM646x - https://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
Keystone - https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
Examples:
wdt: wdt@2320000 {
compatible = "ti,davinci-wdt";
reg = <0x02320000 0x80>;
timeout-sec = <30>;
clocks = <&clkwdtimer0>;
};
Documentation/devicetree/bindings/watchdog/lpc18xx-wdt.txt deleted 100644 → 0
View file @ 19a519ca
* NXP LPC18xx Watchdog Timer (WDT)
Required properties:
- compatible: Should be "nxp,lpc1850-wwdt"
- reg: Should contain WDT registers location and length
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Should contain "wdtclk" and "reg"; the watchdog counter
clock and register interface clock respectively.
- interrupts: Should contain WDT interrupt
Examples:
watchdog@40080000 {
compatible = "nxp,lpc1850-wwdt";
reg = <0x40080000 0x24>;
clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
clock-names = "wdtclk", "reg";
interrupts = <49>;
};
Documentation/devicetree/bindings/watchdog/nxp,lpc1850-wwdt.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/nxp,lpc1850-wwdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC18xx Watchdog Timer (WDT)
maintainers:
- Animesh Agarwal <animeshagarwal28@gmail.com>
properties:
compatible:
const: nxp,lpc1850-wwdt
reg:
maxItems: 1
clocks:
items:
- description: Watchdog counter clock
- description: Register interface clock
clock-names:
items:
- const: wdtclk
- const: reg
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/lpc18xx-cgu.h>
#include <dt-bindings/clock/lpc18xx-ccu.h>
watchdog@40080000 {
compatible = "nxp,lpc1850-wwdt";
reg = <0x40080000 0x24>;
clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
clock-names = "wdtclk", "reg";
interrupts = <49>;
};
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
View file @ 2a17bb8c
......@@ -26,6 +26,7 @@ properties:
- qcom,apss-wdt-msm8994
- qcom,apss-wdt-qcm2290
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sa8255p
- qcom,apss-wdt-sa8775p
- qcom,apss-wdt-sc7180
- qcom,apss-wdt-sc7280
......
Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
View file @ 2a17bb8c
......@@ -29,6 +29,7 @@ properties:
- rockchip,rk3368-wdt
- rockchip,rk3399-wdt
- rockchip,rk3568-wdt
- rockchip,rk3576-wdt
- rockchip,rk3588-wdt
- rockchip,rv1108-wdt
- const: snps,dw-wdt
......
Documentation/devicetree/bindings/watchdog/ti,davinci-wdt.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/ti,davinci-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DaVinci/Keystone Watchdog Timer Controller
maintainers:
- Kousik Sanagavarapu <five231003@gmail.com>
description: |
TI's Watchdog Timer Controller for DaVinci and Keystone Processors.
Datasheets
Davinci DM646x - https://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
Keystone - https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
oneOf:
- items:
- const: ti,keystone-wdt
- const: ti,davinci-wdt
- items:
- const: ti,davinci-wdt
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
wdt: watchdog@22f0080 {
compatible = "ti,keystone-wdt", "ti,davinci-wdt";
reg = <0x022f0080 0x80>;
clocks = <&clkwdtimer0>;
};
...
Documentation/devicetree/bindings/watchdog/zii,rave-wdt.yaml 0 → 100644
View file @ 2a17bb8c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/zii,rave-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zodiac RAVE Watchdog Timer
maintainers:
- Martyn Welch <martyn.welch@collabora.co.uk>
- Guenter Roeck <linux@roeck-us.net>
- Wim Van Sebroeck <wim@iguana.be>
properties:
compatible:
const: zii,rave-wdt
reg:
maxItems: 1
description: i2c slave address of device, usually 0x38
reset-duration-ms:
description:
Duration of the pulse generated when the watchdog times
out.
required:
- compatible
- reg
allOf:
- $ref: watchdog.yaml#
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
watchdog@38 {
compatible = "zii,rave-wdt";
reg = <0x38>;
timeout-sec = <30>;
reset-duration-ms = <30>;
};
};
Documentation/devicetree/bindings/watchdog/ziirave-wdt.txt deleted 100644 → 0
View file @ 19a519ca
Zodiac RAVE Watchdog Timer
Required properties:
- compatible: must be "zii,rave-wdt"
- reg: i2c slave address of device, usually 0x38
Optional Properties:
- timeout-sec: Watchdog timeout value in seconds.
- reset-duration-ms: Duration of the pulse generated when the watchdog times
out. Value in milliseconds.
Example:
watchdog@38 {
compatible = "zii,rave-wdt";
reg = <0x38>;
timeout-sec = <30>;
reset-duration-ms = <30>;
};
MAINTAINERS
View file @ 2a17bb8c
......@@ -2477,6 +2477,7 @@ N: lpc18xx
ARM/LPC32XX SOC SUPPORT
M: Vladimir Zapolskiy <vz@mleia.com>
M: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://github.com/vzapolskiy/linux-lpc32xx.git
......@@ -2489,6 +2490,14 @@ F: drivers/usb/host/ohci-nxp.c
F: drivers/watchdog/pnx4008_wdt.c
N: lpc32xx
LPC32XX DMAMUX SUPPORT
M: J.M.B. Downing <jonathan.downing@nautel.com>
M: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
R: Vladimir Zapolskiy <vz@mleia.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/dma/nxp,lpc3220-dmamux.yaml
ARM/Marvell Dove/MV78xx0/Orion SOC support
M: Andrew Lunn <andrew@lunn.ch>
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
......@@ -14296,8 +14305,8 @@ M: Sean Wang <sean.wang@mediatek.com>
L: linux-bluetooth@vger.kernel.org
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/net/bluetooth/mediatek,bluetooth.txt
F: Documentation/devicetree/bindings/net/bluetooth/mediatek,mt7921s-bluetooth.yaml
F: Documentation/devicetree/bindings/net/mediatek-bluetooth.txt
F: drivers/bluetooth/btmtkuart.c
MEDIATEK BOARD LEVEL SHUTDOWN DRIVERS
......
drivers/of/address.c
View file @ 2a17bb8c
......@@ -8,6 +8,7 @@
#include <linux/logic_pio.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/overflow.h>
#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/sizes.h>
......@@ -197,6 +198,23 @@ static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns,
#endif /* CONFIG_PCI */
static int __of_address_resource_bounds(struct resource *r, u64 start, u64 size)
{
u64 end = start;
if (overflows_type(start, r->start))
return -EOVERFLOW;
if (size && check_add_overflow(end, size - 1, &end))
return -EOVERFLOW;
if (overflows_type(end, r->end))
return -EOVERFLOW;
r->start = start;
r->end = end;
return 0;
}
/*
* of_pci_range_to_resource - Create a resource from an of_pci_range
* @range: the PCI range that describes the resource
......@@ -215,6 +233,7 @@ static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns,
int of_pci_range_to_resource(struct of_pci_range *range,
struct device_node *np, struct resource *res)
{
u64 start;
int err;
res->flags = range->flags;
res->parent = res->child = res->sibling = NULL;
......@@ -231,18 +250,11 @@ int of_pci_range_to_resource(struct of_pci_range *range,
err = -EINVAL;
goto invalid_range;
}
res->start = port;
start = port;
} else {
if ((sizeof(resource_size_t) < 8) &&
upper_32_bits(range->cpu_addr)) {
err = -EINVAL;
goto invalid_range;
}
res->start = range->cpu_addr;
start = range->cpu_addr;
}
res->end = res->start + range->size - 1;
return 0;
return __of_address_resource_bounds(res, start, range->size);
invalid_range:
res->start = (resource_size_t)OF_BAD_ADDR;
......@@ -258,8 +270,8 @@ EXPORT_SYMBOL(of_pci_range_to_resource);
* @res: pointer to a valid resource that will be updated to
* reflect the values contained in the range.
*
* Returns ENOENT if the entry is not found or EINVAL if the range cannot be
* converted to resource.
* Returns -ENOENT if the entry is not found or -EOVERFLOW if the range
* cannot be converted to resource.
*/
int of_range_to_resource(struct device_node *np, int index, struct resource *res)
{
......@@ -1061,12 +1073,10 @@ static int __of_address_to_resource(struct device_node *dev, int index, int bar_
if (of_mmio_is_nonposted(dev))
flags |= IORESOURCE_MEM_NONPOSTED;
r->start = taddr;
r->end = taddr + size - 1;
r->flags = flags;
r->name = name ? name : dev->full_name;
return 0;
return __of_address_resource_bounds(r, taddr, size);
}
/**
......
drivers/of/irq.c
View file @ 2a17bb8c
......@@ -357,8 +357,8 @@ int of_irq_parse_one(struct device_node *device, int index, struct of_phandle_ar
addr = of_get_property(device, "reg", &addr_len);
/* Prevent out-of-bounds read in case of longer interrupt parent address size */
if (addr_len > (3 * sizeof(__be32)))
addr_len = 3 * sizeof(__be32);
if (addr_len > sizeof(addr_buf))
addr_len = sizeof(addr_buf);
if (addr)
memcpy(addr_buf, addr, addr_len);
......@@ -429,9 +429,8 @@ int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
of_property_read_string_index(dev, "interrupt-names", index,
&name);
r->start = r->end = irq;
r->flags = IORESOURCE_IRQ | irqd_get_trigger_type(irq_get_irq_data(irq));
r->name = name ? name : of_node_full_name(dev);
*r = DEFINE_RES_IRQ_NAMED(irq, name ?: of_node_full_name(dev));
r->flags |= irq_get_trigger_type(irq);
}
return irq;
......@@ -716,8 +715,7 @@ struct irq_domain *of_msi_map_get_device_domain(struct device *dev, u32 id,
* @np: device node for @dev
* @token: bus type for this domain
*
* Parse the msi-parent property (both the simple and the complex
* versions), and returns the corresponding MSI domain.
* Parse the msi-parent property and returns the corresponding MSI domain.
*
* Returns: the MSI domain for this device (or NULL on failure).
*/
......@@ -725,33 +723,14 @@ struct irq_domain *of_msi_get_domain(struct device *dev,
struct device_node *np,
enum irq_domain_bus_token token)
{
struct device_node *msi_np;
struct of_phandle_iterator it;
struct irq_domain *d;
int err;
/* Check for a single msi-parent property */
msi_np = of_parse_phandle(np, "msi-parent", 0);
if (msi_np && !of_property_read_bool(msi_np, "#msi-cells")) {
d = irq_find_matching_host(msi_np, token);
if (!d)
of_node_put(msi_np);
return d;
}
if (token == DOMAIN_BUS_PLATFORM_MSI) {
/* Check for the complex msi-parent version */
struct of_phandle_args args;
int index = 0;
while (!of_parse_phandle_with_args(np, "msi-parent",
"#msi-cells",
index, &args)) {
d = irq_find_matching_host(args.np, token);
if (d)
return d;
of_node_put(args.np);
index++;
}
of_for_each_phandle(&it, err, np, "msi-parent", "#msi-cells", 0) {
d = irq_find_matching_host(it.node, token);
if (d)
return d;
}
return NULL;
......
drivers/of/overlay.c
View file @ 2a17bb8c
......@@ -472,7 +472,6 @@ static int add_changeset_node(struct overlay_changeset *ovcs,
static int build_changeset_next_level(struct overlay_changeset *ovcs,
struct target *target, const struct device_node *overlay_node)
{
struct device_node *child;
struct property *prop;
int ret;
......@@ -485,12 +484,11 @@ static int build_changeset_next_level(struct overlay_changeset *ovcs,
}
}
for_each_child_of_node(overlay_node, child) {
for_each_child_of_node_scoped(overlay_node, child) {
ret = add_changeset_node(ovcs, target, child);
if (ret) {
pr_debug("Failed to apply node @%pOF/%pOFn, err=%d\n",
target->np, child, ret);
of_node_put(child);
return ret;
}
}
......@@ -1078,16 +1076,12 @@ EXPORT_SYMBOL_GPL(of_overlay_fdt_apply);
*/
static int find_node(struct device_node *tree, struct device_node *np)
{
struct device_node *child;
if (tree == np)
return 1;
for_each_child_of_node(tree, child) {
if (find_node(child, np)) {
of_node_put(child);
for_each_child_of_node_scoped(tree, child) {
if (find_node(child, np))
return 1;
}
}
return 0;
......
drivers/of/platform.c
View file @ 2a17bb8c
......@@ -338,7 +338,6 @@ static int of_platform_bus_create(struct device_node *bus,
struct device *parent, bool strict)
{
const struct of_dev_auxdata *auxdata;
struct device_node *child;
struct platform_device *dev;
const char *bus_id = NULL;
void *platform_data = NULL;
......@@ -382,13 +381,11 @@ static int of_platform_bus_create(struct device_node *bus,
if (!dev || !of_match_node(matches, bus))
return 0;
for_each_child_of_node(bus, child) {
for_each_child_of_node_scoped(bus, child) {
pr_debug(" create child: %pOF\n", child);
rc = of_platform_bus_create(child, matches, lookup, &dev->dev, strict);
if (rc) {
of_node_put(child);
if (rc)
break;
}
}
of_node_set_flag(bus, OF_POPULATED_BUS);
return rc;
......@@ -459,7 +456,6 @@ int of_platform_populate(struct device_node *root,
const struct of_dev_auxdata *lookup,
struct device *parent)
{
struct device_node *child;
int rc = 0;
root = root ? of_node_get(root) : of_find_node_by_path("/");
......@@ -470,12 +466,10 @@ int of_platform_populate(struct device_node *root,
pr_debug(" starting at: %pOF\n", root);
device_links_supplier_sync_state_pause();
for_each_child_of_node(root, child) {
for_each_child_of_node_scoped(root, child) {
rc = of_platform_bus_create(child, matches, lookup, parent, true);
if (rc) {
of_node_put(child);
if (rc)
break;
}
}
device_links_supplier_sync_state_resume();
......
drivers/of/property.c
View file @ 2a17bb8c
......@@ -452,12 +452,17 @@ EXPORT_SYMBOL_GPL(of_property_read_string);
/**
* of_property_match_string() - Find string in a list and return index
* @np: pointer to node containing string list property
* @np: pointer to the node containing the string list property
* @propname: string list property name
* @string: pointer to string to search for in string list
* @string: pointer to the string to search for in the string list
*
* This function searches a string list property and returns the index
* of a specific string value.
* Search for an exact match of string in a device node property which is a
* string of lists.
*
* Return: the index of the first occurrence of the string on success, -EINVAL
* if the property does not exist, -ENODATA if the property does not have a
* value, and -EILSEQ if the string is not null-terminated within the length of
* the property data.
*/
int of_property_match_string(const struct device_node *np, const char *propname,
const char *string)
......@@ -773,16 +778,11 @@ EXPORT_SYMBOL(of_graph_get_port_parent);
struct device_node *of_graph_get_remote_port_parent(
const struct device_node *node)
{
struct device_node *np, *pp;
/* Get remote endpoint node. */
np = of_graph_get_remote_endpoint(node);
pp = of_graph_get_port_parent(np);
struct device_node *np __free(device_node) =
of_graph_get_remote_endpoint(node);
of_node_put(np);
return pp;
return of_graph_get_port_parent(np);
}
EXPORT_SYMBOL(of_graph_get_remote_port_parent);
......@@ -1064,19 +1064,15 @@ static void of_link_to_phandle(struct device_node *con_np,
struct device_node *sup_np,
u8 flags)
{
struct device_node *tmp_np = of_node_get(sup_np);
struct device_node *tmp_np __free(device_node) = of_node_get(sup_np);
/* Check that sup_np and its ancestors are available. */
while (tmp_np) {
if (of_fwnode_handle(tmp_np)->dev) {
of_node_put(tmp_np);
if (of_fwnode_handle(tmp_np)->dev)
break;
}
if (!of_device_is_available(tmp_np)) {
of_node_put(tmp_np);
if (!of_device_is_available(tmp_np))
return;
}
tmp_np = of_get_next_parent(tmp_np);
}
......@@ -1440,16 +1436,13 @@ static int of_link_property(struct device_node *con_np, const char *prop_name)
}
while ((phandle = s->parse_prop(con_np, prop_name, i))) {
struct device_node *con_dev_np;
struct device_node *con_dev_np __free(device_node) =
s->get_con_dev ? s->get_con_dev(con_np) : of_node_get(con_np);
con_dev_np = s->get_con_dev
? s->get_con_dev(con_np)
: of_node_get(con_np);
matched = true;
i++;
of_link_to_phandle(con_dev_np, phandle, s->fwlink_flags);
of_node_put(phandle);
of_node_put(con_dev_np);
}
s++;
}
......
drivers/of/resolver.c
View file @ 2a17bb8c
......@@ -150,7 +150,7 @@ static int node_name_cmp(const struct device_node *dn1,
static int adjust_local_phandle_references(struct device_node *local_fixups,
struct device_node *overlay, int phandle_delta)
{
struct device_node *child, *overlay_child;
struct device_node *overlay_child;
struct property *prop_fix, *prop;
int err, i, count;
unsigned int off;
......@@ -194,7 +194,7 @@ static int adjust_local_phandle_references(struct device_node *local_fixups,
* The roots of the subtrees are the overlay's __local_fixups__ node
* and the overlay's root node.
*/
for_each_child_of_node(local_fixups, child) {
for_each_child_of_node_scoped(local_fixups, child) {
for_each_child_of_node(overlay, overlay_child)
if (!node_name_cmp(child, overlay_child)) {
......@@ -202,17 +202,13 @@ static int adjust_local_phandle_references(struct device_node *local_fixups,
break;
}
if (!overlay_child) {
of_node_put(child);
if (!overlay_child)
return -EINVAL;
}
err = adjust_local_phandle_references(child, overlay_child,
phandle_delta);
if (err) {
of_node_put(child);
if (err)
return err;
}
}
return 0;
......
drivers/of/unittest.c
View file @ 2a17bb8c
......@@ -900,8 +900,8 @@ static void __init of_unittest_changeset(void)
unittest(!of_find_node_by_path("/testcase-data/changeset/n2/n21"),
"'%pOF' still present after revert\n", n21);
ppremove = of_find_property(parent, "prop-remove", NULL);
unittest(ppremove, "failed to find removed prop after revert\n");
unittest(of_property_present(parent, "prop-remove"),
"failed to find removed prop after revert\n");
ret = of_property_read_string(parent, "prop-update", &propstr);
unittest(!ret, "failed to find updated prop after revert\n");
......
include/dt-bindings/interrupt-controller/arm-gic.h
View file @ 2a17bb8c
......@@ -12,6 +12,8 @@
#define GIC_SPI 0
#define GIC_PPI 1
#define GIC_ESPI 2
#define GIC_EPPI 3
/*
* Interrupt specifier cell 2.
......
scripts/dtc/checks.c
View file @ 2a17bb8c
......@@ -1826,10 +1826,14 @@ static void check_graph_port(struct check *c, struct dt_info *dti,
if (node->bus != &graph_port_bus)
return;
check_graph_reg(c, dti, node);
/* skip checks below for overlays */
if (dti->dtsflags & DTSF_PLUGIN)
return;
if (!strprefixeq(node->name, node->basenamelen, "port"))
FAIL(c, dti, node, "graph port node name should be 'port'");
check_graph_reg(c, dti, node);
}
WARNING(graph_port, check_graph_port, NULL, &graph_nodes);
......@@ -1864,11 +1868,15 @@ static void check_graph_endpoint(struct check *c, struct dt_info *dti,
if (!node->parent || node->parent->bus != &graph_port_bus)
return;
check_graph_reg(c, dti, node);
/* skip checks below for overlays */
if (dti->dtsflags & DTSF_PLUGIN)
return;
if (!strprefixeq(node->name, node->basenamelen, "endpoint"))
FAIL(c, dti, node, "graph endpoint node name should be 'endpoint'");
check_graph_reg(c, dti, node);
remote_node = get_remote_endpoint(c, dti, node);
if (!remote_node)
return;
......
scripts/dtc/dt-extract-compatibles
View file @ 2a17bb8c
......@@ -46,6 +46,15 @@ def parse_of_match_table(data):
return match_table_list
def parse_of_functions(data, func_name):
""" Find all compatibles in the last argument of a given function """
compat_list = []
for m in re.finditer(rf'{func_name}\(([a-zA-Z0-9_>\(\)"\-]+,\s)*"([a-zA-Z0-9_,-]+)"\)', data):
compat_list.append(m[2])
return compat_list
def parse_compatibles(file, compat_ignore_list):
with open(file, 'r', encoding='utf-8') as f:
data = f.read().replace('\n', '')
......@@ -60,6 +69,10 @@ def parse_compatibles(file, compat_ignore_list):
else:
compat_list = parse_of_declare_macros(data)
compat_list += parse_of_device_id(data)
compat_list += parse_of_functions(data, "_is_compatible")
compat_list += parse_of_functions(data, "of_find_compatible_node")
compat_list += parse_of_functions(data, "for_each_compatible_node")
compat_list += parse_of_functions(data, "of_get_compatible_child")
return compat_list
......
scripts/dtc/fdtoverlay.c
View file @ 2a17bb8c
......@@ -48,7 +48,7 @@ static void *apply_one(char *base, const char *overlay, size_t *buf_len,
int ret;
/*
* We take a copies first, because a failed apply can trash
* We take copies first, because a failed apply can trash
* both the base blob and the overlay
*/
tmpo = xmalloc(fdt_totalsize(overlay));
......
scripts/dtc/version_gen.h
View file @ 2a17bb8c
#define DTC_VERSION "DTC 1.7.0-g1df7b047"
#define DTC_VERSION "DTC 1.7.0-gbcd02b52"
tools/testing/selftests/dt/test_unprobed_devices.sh
View file @ 2a17bb8c
......@@ -34,8 +34,21 @@ nodes_compatible=$(
# Check if node is available
if [[ -e "${node}"/status ]]; then
status=$(tr -d '\000' < "${node}"/status)
[[ "${status}" != "okay" && "${status}" != "ok" ]] && continue
if [[ "${status}" != "okay" && "${status}" != "ok" ]]; then
if [ -n "${disabled_nodes_regex}" ]; then
disabled_nodes_regex="${disabled_nodes_regex}|${node}"
else
disabled_nodes_regex="${node}"
fi
continue
fi
fi
# Ignore this node if one of its ancestors was disabled
if [ -n "${disabled_nodes_regex}" ]; then
echo "${node}" | grep -q -E "${disabled_nodes_regex}" && continue
fi
echo "${node}" | sed -e 's|\/proc\/device-tree||'
done | sort
)
......
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