drm/nouveau/kms/nv04-: no need for multiple nvsw objects

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>

drivers/gpu/drm/nouveau/dispnv04/disp.c

@@ -31,6 +31,7 @@
 #include "nouveau_connector.h"
 #include "nouveau_bo.h"
 #include "nouveau_gem.h"
+#include "nouveau_chan.h"
 
 #include <nvif/if0004.h>
 
@@ -214,8 +215,8 @@ nv04_display_create(struct drm_device *dev)
 	dev->driver_features &= ~DRIVER_ATOMIC;
 
 	/* Request page flip completion event. */
-	if (drm->nvsw.client) {
-		nvif_notify_ctor(&drm->nvsw, "kmsFlip", nv04_flip_complete,
+	if (drm->channel) {
+		nvif_notify_ctor(&drm->channel->nvsw, "kmsFlip", nv04_flip_complete,
 				 false, NV04_NVSW_NTFY_UEVENT,
 				 NULL, 0, 0, &disp->flip);
 	}

drivers/gpu/drm/nouveau/nouveau_drm.c

@@ -331,7 +331,6 @@ nouveau_accel_gr_fini(struct nouveau_drm *drm)
 	nouveau_channel_idle(drm->channel);
 	nvif_object_dtor(&drm->ntfy);
 	nvkm_gpuobj_del(&drm->notify);
-	nvif_object_dtor(&drm->nvsw);
 	nouveau_channel_del(&drm->channel);
 }
 
@@ -363,15 +362,15 @@ nouveau_accel_gr_init(struct nouveau_drm *drm)
 	 * synchronisation of page flips, as well as to implement fences
 	 * on TNT/TNT2 HW that lacks any kind of support in host.
 	 */
-	if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
+	if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 		ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
 				       NVDRM_NVSW, nouveau_abi16_swclass(drm),
-				       NULL, 0, &drm->nvsw);
+				       NULL, 0, &drm->channel->nvsw);
 		if (ret == 0) {
 			ret = RING_SPACE(drm->channel, 2);
 			if (ret == 0) {
 				BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
-				OUT_RING  (drm->channel, drm->nvsw.handle);
+				OUT_RING  (drm->channel, drm->channel->nvsw.handle);
 			}
 		}
 

drivers/gpu/drm/nouveau/nouveau_drv.h

@@ -186,7 +186,6 @@ struct nouveau_drm {
 	struct nouveau_channel *channel;
 	struct nvkm_gpuobj *notify;
 	struct nouveau_fbdev *fbcon;
-	struct nvif_object nvsw;
 	struct nvif_object ntfy;
 
 	/* nv10-nv40 tiling regions */