Commit 2c58a914 authored by Jakub Kicinski's avatar Jakub Kicinski

Merge branch 'mlxsw-remove-some-unused-code'

Petr Machata says:

====================
mlxsw: Remove some unused code

This patchset removes code that is not used anymore after the following two
commits removed all users:

- commit b0d80c01 ("mlxsw: Remove Mellanox SwitchX-2 ASIC support")
- commit 9b43fbb8 ("mlxsw: Remove Mellanox SwitchIB ASIC support")
====================

Link: https://lore.kernel.org/r/cover.1661350629.git.petrm@nvidia.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents bace3f46 12be3edf
......@@ -1307,21 +1307,6 @@ mlxsw_devlink_sb_pool_set(struct devlink *devlink,
extack);
}
static int mlxsw_devlink_port_type_set(struct devlink_port *devlink_port,
enum devlink_port_type port_type)
{
struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
if (!mlxsw_driver->port_type_set)
return -EOPNOTSUPP;
return mlxsw_driver->port_type_set(mlxsw_core,
mlxsw_core_port->local_port,
port_type);
}
static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port,
unsigned int sb_index, u16 pool_index,
u32 *p_threshold)
......@@ -1652,7 +1637,6 @@ static const struct devlink_ops mlxsw_devlink_ops = {
BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE),
.reload_down = mlxsw_devlink_core_bus_device_reload_down,
.reload_up = mlxsw_devlink_core_bus_device_reload_up,
.port_type_set = mlxsw_devlink_port_type_set,
.port_split = mlxsw_devlink_port_split,
.port_unsplit = mlxsw_devlink_port_unsplit,
.sb_pool_get = mlxsw_devlink_sb_pool_get,
......@@ -3183,18 +3167,6 @@ void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u16 local_port,
}
EXPORT_SYMBOL(mlxsw_core_port_eth_set);
void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u16 local_port,
void *port_driver_priv)
{
struct mlxsw_core_port *mlxsw_core_port =
&mlxsw_core->ports[local_port];
struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
mlxsw_core_port->port_driver_priv = port_driver_priv;
devlink_port_type_ib_set(devlink_port, NULL);
}
EXPORT_SYMBOL(mlxsw_core_port_ib_set);
void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port,
void *port_driver_priv)
{
......@@ -3207,18 +3179,6 @@ void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port,
}
EXPORT_SYMBOL(mlxsw_core_port_clear);
enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core,
u16 local_port)
{
struct mlxsw_core_port *mlxsw_core_port =
&mlxsw_core->ports[local_port];
struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
return devlink_port->type;
}
EXPORT_SYMBOL(mlxsw_core_port_type_get);
struct devlink_port *
mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core,
u16 local_port)
......
......@@ -264,12 +264,8 @@ int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core,
void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core);
void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u16 local_port,
void *port_driver_priv, struct net_device *dev);
void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u16 local_port,
void *port_driver_priv);
void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port,
void *port_driver_priv);
enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core,
u16 local_port);
struct devlink_port *
mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core,
u16 local_port);
......@@ -349,8 +345,6 @@ struct mlxsw_driver {
const struct mlxsw_bus_info *mlxsw_bus_info,
struct netlink_ext_ack *extack);
void (*fini)(struct mlxsw_core *mlxsw_core);
int (*port_type_set)(struct mlxsw_core *mlxsw_core, u16 local_port,
enum devlink_port_type new_type);
int (*port_split)(struct mlxsw_core *mlxsw_core, u16 local_port,
unsigned int count, struct netlink_ext_ack *extack);
int (*port_unsplit)(struct mlxsw_core *mlxsw_core, u16 local_port,
......
......@@ -4729,25 +4729,6 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
*/
MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
/* reg_ptys_ib_link_width_cap
* IB port supported widths.
* Access: RO
*/
MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
/* reg_ptys_ib_proto_cap
* IB port supported speeds and protocols.
* Access: RO
*/
MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
/* reg_ptys_ext_eth_proto_admin
* Extended speed and protocol to set port to.
* Access: RW
......@@ -4760,18 +4741,6 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
*/
MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
/* reg_ptys_ib_link_width_admin
* IB width to set port to.
* Access: RW
*/
MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
/* reg_ptys_ib_proto_admin
* IB speeds and protocols to set port to.
* Access: RW
*/
MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
/* reg_ptys_ext_eth_proto_oper
* The extended current speed and protocol configured for the port.
* Access: RO
......@@ -4784,18 +4753,6 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
*/
MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
/* reg_ptys_ib_link_width_oper
* The current IB width to set port to.
* Access: RO
*/
MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
/* reg_ptys_ib_proto_oper
* The current IB speed and protocol.
* Access: RO
*/
MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
enum mlxsw_reg_ptys_connector_type {
MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
......@@ -4866,33 +4823,6 @@ static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
}
static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port,
u16 proto_admin, u16 link_width)
{
MLXSW_REG_ZERO(ptys, payload);
mlxsw_reg_ptys_local_port_set(payload, local_port);
mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
}
static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
u16 *p_ib_link_width_cap,
u16 *p_ib_proto_oper,
u16 *p_ib_link_width_oper)
{
if (p_ib_proto_cap)
*p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
if (p_ib_link_width_cap)
*p_ib_link_width_cap =
mlxsw_reg_ptys_ib_link_width_cap_get(payload);
if (p_ib_proto_oper)
*p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
if (p_ib_link_width_oper)
*p_ib_link_width_oper =
mlxsw_reg_ptys_ib_link_width_oper_get(payload);
}
/* PPAD - Port Physical Address Register
* -------------------------------------
* The PPAD register configures the per port physical MAC address.
......@@ -5666,27 +5596,6 @@ static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port,
mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
}
/* PLIB - Port Local to InfiniBand Port
* ------------------------------------
* The PLIB register performs mapping from Local Port into InfiniBand Port.
*/
#define MLXSW_REG_PLIB_ID 0x500A
#define MLXSW_REG_PLIB_LEN 0x10
MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
/* reg_plib_local_port
* Local port number.
* Access: Index
*/
MLXSW_ITEM32_LP(reg, plib, 0x00, 16, 0x00, 12);
/* reg_plib_ib_port
* InfiniBand port remapping for local_port.
* Access: RW
*/
MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
/* PPTB - Port Prio To Buffer Register
* -----------------------------------
* Configures the switch priority to buffer table.
......@@ -12962,7 +12871,6 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(paos),
MLXSW_REG(pfcc),
MLXSW_REG(ppcnt),
MLXSW_REG(plib),
MLXSW_REG(pptb),
MLXSW_REG(pbmc),
MLXSW_REG(pspa),
......
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