Commit 31b1fed3 authored by Yakir Yang's avatar Yakir Yang Committed by Heiko Stuebner

clk: rockchip: add the new clock ids for RK3228 VOP

There are four clocks that vop module would need to operate:
    DCLK_VOP,  HCLK_VOP,  SCLK_VOP,  ACLK_VOP,
Signed-off-by: default avatarYakir Yang <ykk@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 3629e70b
......@@ -50,10 +50,15 @@
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO_SAMPLE 119
#define SCLK_EMMC_SAMPLE 121
#define SCLK_VOP 122
/* dclk gates */
#define DCLK_VOP 190
/* aclk gates */
#define ACLK_DMAC 194
#define ACLK_PERI 210
#define ACLK_VOP 211
/* pclk gates */
#define PCLK_GPIO0 320
......@@ -75,6 +80,7 @@
#define PCLK_PERI 363
/* hclk gates */
#define HCLK_VOP 452
#define HCLK_NANDC 453
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
......
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