Commit 3424a00f authored by Larry Finger's avatar Larry Finger Committed by Kalle Valo

rtlwifi: rtl8192c-common: Convert driver to use common DM table initialization

These changes convert both rtl8192ce and rtl8192cu to use the new routine.
Some additional definitions are needed in the core, thus several of the
headers for other drivers are affected, but no other executable code is
changed.
Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent b5d4478d
...@@ -1878,6 +1878,7 @@ void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igvalue) ...@@ -1878,6 +1878,7 @@ void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igvalue)
struct dig_t *dm_digtable = &rtlpriv->dm_digtable; struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
dm_digtable->dig_enable_flag = true; dm_digtable->dig_enable_flag = true;
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
dm_digtable->cur_igvalue = cur_igvalue; dm_digtable->cur_igvalue = cur_igvalue;
dm_digtable->pre_igvalue = 0; dm_digtable->pre_igvalue = 0;
dm_digtable->cur_sta_cstate = DIG_STA_DISCONNECT; dm_digtable->cur_sta_cstate = DIG_STA_DISCONNECT;
...@@ -1903,5 +1904,7 @@ void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igvalue) ...@@ -1903,5 +1904,7 @@ void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igvalue)
dm_digtable->media_connect_1 = false; dm_digtable->media_connect_1 = false;
rtlpriv->dm.dm_initialgain_enable = true; rtlpriv->dm.dm_initialgain_enable = true;
dm_digtable->bt30_cur_igi = 0x32; dm_digtable->bt30_cur_igi = 0x32;
dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
} }
EXPORT_SYMBOL(rtl_dm_diginit); EXPORT_SYMBOL(rtl_dm_diginit);
...@@ -46,6 +46,22 @@ ...@@ -46,6 +46,22 @@
#define DM_DIG_BACKOFF_MIN -4 #define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10 #define DM_DIG_BACKOFF_DEFAULT 10
enum cck_packet_detection_threshold {
CCK_PD_STAGE_LOWRSSI = 0,
CCK_PD_STAGE_HIGHRSSI = 1,
CCK_FA_STAGE_LOW = 2,
CCK_FA_STAGE_HIGH = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
enum dm_dig_connect_e { enum dm_dig_connect_e {
DIG_STA_DISCONNECT, DIG_STA_DISCONNECT,
DIG_STA_CONNECT, DIG_STA_CONNECT,
......
...@@ -249,14 +249,6 @@ enum tag_dynamic_init_gain_operation_type_definition { ...@@ -249,14 +249,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
DIG_OP_TYPE_MAX DIG_OP_TYPE_MAX
}; };
enum tag_cck_packet_detection_threshold_type_definition {
CCK_PD_STAGE_LOWRSSI = 0,
CCK_PD_STAGE_HIGHRSSI = 1,
CCK_FA_STAGE_LOW = 2,
CCK_FA_STAGE_HIGH = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_1r_cca_e { enum dm_1r_cca_e {
CCA_1R = 0, CCA_1R = 0,
CCA_2R = 1, CCA_2R = 1,
...@@ -275,14 +267,6 @@ enum dm_sw_ant_switch_e { ...@@ -275,14 +267,6 @@ enum dm_sw_ant_switch_e {
ANS_ANTENNA_MAX = 3, ANS_ANTENNA_MAX = 3,
}; };
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
enum pwr_track_control_method { enum pwr_track_control_method {
BBSWING, BBSWING,
TXAGC TXAGC
......
...@@ -195,36 +195,6 @@ void dm_savepowerindex(struct ieee80211_hw *hw) ...@@ -195,36 +195,6 @@ void dm_savepowerindex(struct ieee80211_hw *hw)
} }
EXPORT_SYMBOL_GPL(dm_savepowerindex); EXPORT_SYMBOL_GPL(dm_savepowerindex);
static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
dm_digtable->dig_enable_flag = true;
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
dm_digtable->cur_igvalue = 0x20;
dm_digtable->pre_igvalue = 0x0;
dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
dm_digtable->rx_gain_max = DM_DIG_MAX;
dm_digtable->rx_gain_min = DM_DIG_MIN;
dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_LowRssi;
dm_digtable->forbidden_igi = DM_DIG_MIN;
dm_digtable->large_fa_hit = 0;
dm_digtable->recover_cnt = 0;
dm_digtable->dig_min_0 = 0x25;
}
static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
{ {
struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_priv *rtlpriv = rtl_priv(hw);
...@@ -508,27 +478,27 @@ static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) ...@@ -508,27 +478,27 @@ static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
if (dm_digtable->rssi_val_min > 100) if (dm_digtable->rssi_val_min > 100)
dm_digtable->rssi_val_min = 100; dm_digtable->rssi_val_min = 100;
if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) { if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
if (dm_digtable->rssi_val_min <= 25) if (dm_digtable->rssi_val_min <= 25)
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_LowRssi; CCK_PD_STAGE_LOWRSSI;
else else
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_HighRssi; CCK_PD_STAGE_HIGHRSSI;
} else { } else {
if (dm_digtable->rssi_val_min <= 20) if (dm_digtable->rssi_val_min <= 20)
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_LowRssi; CCK_PD_STAGE_LOWRSSI;
else else
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_HighRssi; CCK_PD_STAGE_HIGHRSSI;
} }
} else { } else {
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
} }
if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) || if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) ||
(dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX)) (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX))
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
else else
...@@ -1375,7 +1345,7 @@ void rtl92c_dm_init(struct ieee80211_hw *hw) ...@@ -1375,7 +1345,7 @@ void rtl92c_dm_init(struct ieee80211_hw *hw)
rtlpriv->dm.undec_sm_pwdb = -1; rtlpriv->dm.undec_sm_pwdb = -1;
rtlpriv->dm.undec_sm_cck = -1; rtlpriv->dm.undec_sm_cck = -1;
rtlpriv->dm.dm_initialgain_enable = true; rtlpriv->dm.dm_initialgain_enable = true;
rtl92c_dm_diginit(hw); rtl_dm_diginit(hw, 0x20);
rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE; rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE;
rtl92c_dm_init_dynamic_txpower(hw); rtl92c_dm_init_dynamic_txpower(hw);
......
...@@ -110,14 +110,6 @@ enum tag_dynamic_init_gain_operation_type_definition { ...@@ -110,14 +110,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
DIG_OP_TYPE_MAX DIG_OP_TYPE_MAX
}; };
enum tag_cck_packet_detection_threshold_type_definition {
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_FA_STAGE_Low = 2,
CCK_FA_STAGE_High = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_1r_cca_e { enum dm_1r_cca_e {
CCA_1R = 0, CCA_1R = 0,
CCA_2R = 1, CCA_2R = 1,
...@@ -136,14 +128,6 @@ enum dm_sw_ant_switch_e { ...@@ -136,14 +128,6 @@ enum dm_sw_ant_switch_e {
ANS_ANTENNA_MAX = 3, ANS_ANTENNA_MAX = 3,
}; };
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
void rtl92c_dm_init(struct ieee80211_hw *hw); void rtl92c_dm_init(struct ieee80211_hw *hw);
void rtl92c_dm_watchdog(struct ieee80211_hw *hw); void rtl92c_dm_watchdog(struct ieee80211_hw *hw);
void rtl92c_dm_write_dig(struct ieee80211_hw *hw); void rtl92c_dm_write_dig(struct ieee80211_hw *hw);
......
...@@ -95,14 +95,6 @@ enum tag_dynamic_init_gain_operation_type_definition { ...@@ -95,14 +95,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
DIG_OP_TYPE_MAX DIG_OP_TYPE_MAX
}; };
enum tag_cck_packet_detection_threshold_type_definition {
CCK_PD_STAGE_LOWRSSI = 0,
CCK_PD_STAGE_HIGHRSSI = 1,
CCK_FA_STAGE_LOW = 2,
CCK_FA_STAGE_HIGH = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_1r_cca { enum dm_1r_cca {
CCA_1R = 0, CCA_1R = 0,
CCA_2R = 1, CCA_2R = 1,
...@@ -121,14 +113,6 @@ enum dm_sw_ant_switch { ...@@ -121,14 +113,6 @@ enum dm_sw_ant_switch {
ANS_ANTENNA_MAX = 3, ANS_ANTENNA_MAX = 3,
}; };
enum dm_dig_ext_port_alg {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
void rtl92d_dm_init(struct ieee80211_hw *hw); void rtl92d_dm_init(struct ieee80211_hw *hw);
void rtl92d_dm_watchdog(struct ieee80211_hw *hw); void rtl92d_dm_watchdog(struct ieee80211_hw *hw);
void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw); void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw);
......
...@@ -54,14 +54,6 @@ enum dm_dig_sta { ...@@ -54,14 +54,6 @@ enum dm_dig_sta {
DM_STA_DIG_MAX DM_STA_DIG_MAX
}; };
enum dm_dig_ext_port_alg {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
enum dm_ratr_sta { enum dm_ratr_sta {
DM_RATR_STA_HIGH = 0, DM_RATR_STA_HIGH = 0,
DM_RATR_STA_MIDDLEHIGH = 1, DM_RATR_STA_MIDDLEHIGH = 1,
......
...@@ -396,30 +396,30 @@ static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) ...@@ -396,30 +396,30 @@ static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw); dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw);
if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) { if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
if (dm_digtable->rssi_val_min <= 25) if (dm_digtable->rssi_val_min <= 25)
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_LowRssi; CCK_PD_STAGE_LOWRSSI;
else else
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_HighRssi; CCK_PD_STAGE_HIGHRSSI;
} else { } else {
if (dm_digtable->rssi_val_min <= 20) if (dm_digtable->rssi_val_min <= 20)
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_LowRssi; CCK_PD_STAGE_LOWRSSI;
else else
dm_digtable->cur_cck_pd_state = dm_digtable->cur_cck_pd_state =
CCK_PD_STAGE_HighRssi; CCK_PD_STAGE_HIGHRSSI;
} }
} else { } else {
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
} }
if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) { if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800) if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
dm_digtable->cur_cck_fa_state = dm_digtable->cur_cck_fa_state =
CCK_FA_STAGE_High; CCK_FA_STAGE_HIGH;
else else
dm_digtable->cur_cck_fa_state = dm_digtable->cur_cck_fa_state =
CCK_FA_STAGE_LOW; CCK_FA_STAGE_LOW;
......
...@@ -95,14 +95,6 @@ enum tag_dynamic_init_gain_operation_type_definition { ...@@ -95,14 +95,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
DIG_OP_TYPE_MAX DIG_OP_TYPE_MAX
}; };
enum tag_cck_packet_detection_threshold_type_definition {
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_FA_STAGE_LOW = 2,
CCK_FA_STAGE_High = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_1r_cca_e { enum dm_1r_cca_e {
CCA_1R = 0, CCA_1R = 0,
CCA_2R = 1, CCA_2R = 1,
...@@ -121,14 +113,6 @@ enum dm_sw_ant_switch_e { ...@@ -121,14 +113,6 @@ enum dm_sw_ant_switch_e {
ANS_ANTENNA_MAX = 3, ANS_ANTENNA_MAX = 3,
}; };
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1) #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1) #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1) #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
......
...@@ -239,14 +239,6 @@ enum dm_sw_ant_switch_e { ...@@ -239,14 +239,6 @@ enum dm_sw_ant_switch_e {
ANS_ANTENNA_MAX = 3, ANS_ANTENNA_MAX = 3,
}; };
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
enum pwr_track_control_method { enum pwr_track_control_method {
BBSWING, BBSWING,
TXAGC TXAGC
......
...@@ -255,14 +255,6 @@ enum tag_dynamic_init_gain_operation_type_definition { ...@@ -255,14 +255,6 @@ enum tag_dynamic_init_gain_operation_type_definition {
DIG_OP_TYPE_MAX DIG_OP_TYPE_MAX
}; };
enum tag_cck_packet_detection_threshold_type_definition {
CCK_PD_STAGE_LOWRSSI = 0,
CCK_PD_STAGE_HIGHRSSI = 1,
CCK_FA_STAGE_LOW = 2,
CCK_FA_STAGE_HIGH = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_1r_cca_e { enum dm_1r_cca_e {
CCA_1R = 0, CCA_1R = 0,
CCA_2R = 1, CCA_2R = 1,
...@@ -281,14 +273,6 @@ enum dm_sw_ant_switch_e { ...@@ -281,14 +273,6 @@ enum dm_sw_ant_switch_e {
ANS_ANTENNA_MAX = 3, ANS_ANTENNA_MAX = 3,
}; };
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
enum pwr_track_control_method { enum pwr_track_control_method {
BBSWING, BBSWING,
TXAGC, TXAGC,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment