Commit 3529e041 authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu

Blackfin arch: update anomaly lists to match latest sheets

Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 6a87d29b
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
...@@ -37,8 +37,6 @@ ...@@ -37,8 +37,6 @@
#define ANOMALY_05000265 (1) #define ANOMALY_05000265 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (ANOMALY_BF527)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 2) #define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
/* Incorrect Access of OTP_STATUS During otp_write() Function */ /* Incorrect Access of OTP_STATUS During otp_write() Function */
...@@ -153,6 +151,8 @@ ...@@ -153,6 +151,8 @@
#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
#define ANOMALY_05000432 (ANOMALY_BF526) #define ANOMALY_05000432 (ANOMALY_BF526)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
...@@ -168,6 +168,7 @@ ...@@ -168,6 +168,7 @@
#define ANOMALY_05000285 (0) #define ANOMALY_05000285 (0)
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
......
...@@ -194,6 +194,8 @@ ...@@ -194,6 +194,8 @@
#define ANOMALY_05000403 (1) #define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */ /* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1) #define ANOMALY_05000416 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are /* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible. * here to show running on older silicon just isn't feasible.
......
...@@ -148,6 +148,8 @@ ...@@ -148,6 +148,8 @@
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1) #define ANOMALY_05000403 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
#define _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_
#if __SILICON_REVISION__ < 4 #if __SILICON_REVISION__ < 4
# error will not work on BF538 silicon version 0.0, 0.1, 0.2 or 0.3 # error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3
#endif #endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
...@@ -106,16 +106,18 @@ ...@@ -106,16 +106,18 @@
#define ANOMALY_05000403 (1) #define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */ /* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1) #define ANOMALY_05000416 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000230 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000353 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000386 (1)
#endif #endif
...@@ -157,6 +157,8 @@ ...@@ -157,6 +157,8 @@
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */ /* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
......
...@@ -264,6 +264,8 @@ ...@@ -264,6 +264,8 @@
#define ANOMALY_05000371 (1) #define ANOMALY_05000371 (1)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1) #define ANOMALY_05000403 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
......
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