Commit 37f04581 authored by Doug Thompson's avatar Doug Thompson Committed by Linus Torvalds

[PATCH] EDAC: PCI device to DEVICE cleanup

Change MC drivers from using CVS revision strings for their version number,
Now each driver has its own local string.

Remove some PCI dependencies from the core EDAC module.  Made the code 'struct
device' centric instead of 'struct pci_dev' Most of the code changes here are
from a patch by Dave Jiang.  It may be best to eventually move the
PCI-specific code into a separate source file.
Signed-off-by: default avatarDoug Thompson <norsk5@xmission.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent dc474c89
......@@ -20,6 +20,9 @@
#include <linux/slab.h>
#include "edac_mc.h"
#define AMD76X_REVISION " Ver: 2.0.0 " __DATE__
#define amd76x_printk(level, fmt, arg...) \
edac_printk(level, "amd76x", fmt, ##arg)
......@@ -102,15 +105,18 @@ static const struct amd76x_dev_info amd76x_devs[] = {
static void amd76x_get_error_info(struct mem_ctl_info *mci,
struct amd76x_error_info *info)
{
pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
struct pci_dev *pdev;
pdev = to_pci_dev(mci->dev);
pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
&info->ecc_mode_status);
if (info->ecc_mode_status & BIT(8))
pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
(u32) BIT(8), (u32) BIT(8));
if (info->ecc_mode_status & BIT(9))
pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
(u32) BIT(9), (u32) BIT(9));
}
......@@ -211,13 +217,13 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
}
debugf0("%s(): mci = %p\n", __func__, mci);
mci->pdev = pdev;
mci->dev = &pdev->dev;
mci->mtype_cap = MEM_FLAG_RDDR;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
mci->edac_cap = ems_mode ?
(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
mci->mod_name = EDAC_MOD_STR;
mci->mod_ver = "$Revision: 1.4.2.5 $";
mci->mod_ver = AMD76X_REVISION;
mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
mci->edac_check = amd76x_check;
mci->ctl_page_to_phys = NULL;
......@@ -230,7 +236,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
u32 dms;
/* find the DRAM Chip Select Base address and mask */
pci_read_config_dword(mci->pdev,
pci_read_config_dword(pdev,
AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
if (!(mba & BIT(0)))
......@@ -238,8 +244,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
mba_base = mba & 0xff800000UL;
mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
&dms);
pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
csrow->first_page = mba_base >> PAGE_SHIFT;
csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
......@@ -291,7 +296,7 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev)
debugf0("%s()\n", __func__);
if ((mci = edac_mc_del_mc(pdev)) == NULL)
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
return;
edac_mc_free(mci);
......
......@@ -25,6 +25,8 @@
#include <linux/slab.h>
#include "edac_mc.h"
#define E752X_REVISION " Ver: 2.0.0 " __DATE__
static int force_function_unhide;
#define e752x_printk(level, fmt, arg...) \
......@@ -819,8 +821,8 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
EDAC_FLAG_S4ECD4ED;
/* FIXME - what if different memory types are in different csrows? */
mci->mod_name = EDAC_MOD_STR;
mci->mod_ver = "$Revision: 1.5.2.11 $";
mci->pdev = pdev;
mci->mod_ver = E752X_REVISION;
mci->dev = &pdev->dev;
debugf3("%s(): init pvt\n", __func__);
pvt = (struct e752x_pvt *) mci->pvt_info;
......@@ -864,7 +866,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
struct csrow_info *csrow = &mci->csrows[index];
mem_dev = (mem_dev == 2);
pci_read_config_byte(mci->pdev, E752X_DRB + index, &value);
pci_read_config_byte(pdev, E752X_DRB + index, &value);
/* convert a 128 or 64 MiB DRB to a page size. */
cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
......@@ -904,8 +906,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
u8 row = 0;
for (index = 0; index < 8; index += 2) {
pci_read_config_byte(mci->pdev, E752X_DRB + index,
&value);
pci_read_config_byte(pdev, E752X_DRB + index, &value);
/* test if there is a dimm in this slot */
if (value == last) {
......@@ -918,7 +919,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
last = value;
/* test the next value to see if the dimm is
double sided */
pci_read_config_byte(mci->pdev,
pci_read_config_byte(pdev,
E752X_DRB + index + 1,
&value);
pvt->map[index + 1] = (value == last) ?
......@@ -935,18 +936,18 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
}
/* set the map type. 1 = normal, 0 = reversed */
pci_read_config_byte(mci->pdev, E752X_DRM, &stat8);
pci_read_config_byte(pdev, E752X_DRM, &stat8);
pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
mci->edac_cap |= EDAC_FLAG_NONE;
debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
/* load the top of low memory, remap base, and remap limit vars */
pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data);
pci_read_config_word(pdev, E752X_TOLM, &pci_data);
pvt->tolm = ((u32) pci_data) << 4;
pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data);
pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
pvt->remapbase = ((u32) pci_data) << 14;
pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data);
pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
pvt->remaplimit = ((u32) pci_data) << 14;
e752x_printk(KERN_INFO,
"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
......@@ -1015,7 +1016,7 @@ static void __devexit e752x_remove_one(struct pci_dev *pdev)
debugf0("%s()\n", __func__);
if ((mci = edac_mc_del_mc(pdev)) == NULL)
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
return;
pvt = (struct e752x_pvt *) mci->pvt_info;
......
......@@ -30,6 +30,8 @@
#include <linux/slab.h>
#include "edac_mc.h"
#define E7XXX_REVISION " Ver: 2.0.0 " __DATE__
#define e7xxx_printk(level, fmt, arg...) \
edac_printk(level, "e7xxx", fmt, ##arg)
......@@ -373,8 +375,8 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
EDAC_FLAG_S4ECD4ED;
/* FIXME - what if different memory types are in different csrows? */
mci->mod_name = EDAC_MOD_STR;
mci->mod_ver = "$Revision: 1.5.2.9 $";
mci->pdev = pdev;
mci->mod_ver = E7XXX_REVISION;
mci->dev = &pdev->dev;
debugf3("%s(): init pvt\n", __func__);
pvt = (struct e7xxx_pvt *) mci->pvt_info;
......@@ -411,7 +413,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
int mem_dev = (dra >> (index * 4 + 3)) & 0x1;
struct csrow_info *csrow = &mci->csrows[index];
pci_read_config_byte(mci->pdev, E7XXX_DRB + index, &value);
pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
/* convert a 64 or 32 MiB DRB to a page size. */
cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
......@@ -448,11 +450,11 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
/* load the top of low memory, remap base, and remap limit vars */
pci_read_config_word(mci->pdev, E7XXX_TOLM, &pci_data);
pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
pvt->tolm = ((u32) pci_data) << 4;
pci_read_config_word(mci->pdev, E7XXX_REMAPBASE, &pci_data);
pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
pvt->remapbase = ((u32) pci_data) << 14;
pci_read_config_word(mci->pdev, E7XXX_REMAPLIMIT, &pci_data);
pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
pvt->remaplimit = ((u32) pci_data) << 14;
e7xxx_printk(KERN_INFO,
"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
......@@ -498,7 +500,7 @@ static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
debugf0("%s()\n", __func__);
if ((mci = edac_mc_del_mc(pdev)) == NULL)
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
return;
pvt = (struct e7xxx_pvt *) mci->pvt_info;
......
This diff is collapsed.
......@@ -88,6 +88,12 @@ extern int edac_debug_level;
#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
PCI_DEVICE_ID_ ## vend ## _ ## dev
#if defined(CONFIG_X86) && defined(CONFIG_PCI)
#define dev_name(dev) pci_name(to_pci_dev(dev))
#else
#define dev_name(dev) to_platform_device(dev)->name
#endif
/* memory devices */
enum dev_type {
DEV_UNKNOWN = 0,
......@@ -327,10 +333,10 @@ struct mem_ctl_info {
struct csrow_info *csrows;
/*
* FIXME - what about controllers on other busses? - IDs must be
* unique. pdev pointer should be sufficiently unique, but
* unique. dev pointer should be sufficiently unique, but
* BUS:SLOT.FUNC numbers may not be unique.
*/
struct pci_dev *pdev;
struct device *dev;
const char *mod_name;
const char *mod_ver;
const char *ctl_name;
......@@ -353,6 +359,8 @@ struct mem_ctl_info {
struct completion kobj_complete;
};
#ifdef CONFIG_PCI
/* write all or some bits in a byte-register*/
static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
u8 mask)
......@@ -401,6 +409,8 @@ static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
pci_write_config_dword(pdev, offset, value);
}
#endif /* CONFIG_PCI */
#ifdef CONFIG_EDAC_DEBUG
void edac_mc_dump_channel(struct channel_info *chan);
void edac_mc_dump_mci(struct mem_ctl_info *mci);
......@@ -408,7 +418,7 @@ void edac_mc_dump_csrow(struct csrow_info *csrow);
#endif /* CONFIG_EDAC_DEBUG */
extern int edac_mc_add_mc(struct mem_ctl_info *mci);
extern struct mem_ctl_info * edac_mc_del_mc(struct pci_dev *pdev);
extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
unsigned long page);
extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
......
......@@ -17,6 +17,8 @@
#include <linux/slab.h>
#include "edac_mc.h"
#define I82860_REVISION " Ver: 2.0.0 " __DATE__
#define i82860_printk(level, fmt, arg...) \
edac_printk(level, "i82860", fmt, ##arg)
......@@ -63,17 +65,21 @@ static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code
static void i82860_get_error_info(struct mem_ctl_info *mci,
struct i82860_error_info *info)
{
struct pci_dev *pdev;
pdev = to_pci_dev(mci->dev);
/*
* This is a mess because there is no atomic way to read all the
* registers at once and the registers can transition from CE being
* overwritten by UE.
*/
pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts);
pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
pci_read_config_word(mci->pdev, I82860_DERRCTL_STS, &info->derrsyn);
pci_read_config_word(mci->pdev, I82860_ERRSTS, &info->errsts2);
pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
pci_read_config_dword(pdev, I82860_EAP, &info->eap);
pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);
pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
/*
* If the error is the same for both reads then the first set of reads
......@@ -84,8 +90,8 @@ static void i82860_get_error_info(struct mem_ctl_info *mci,
return;
if ((info->errsts ^ info->errsts2) & 0x0003) {
pci_read_config_dword(mci->pdev, I82860_EAP, &info->eap);
pci_read_config_word(mci->pdev, I82860_DERRCTL_STS,
pci_read_config_dword(pdev, I82860_EAP, &info->eap);
pci_read_config_word(pdev, I82860_DERRCTL_STS,
&info->derrsyn);
}
}
......@@ -151,7 +157,7 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
return -ENOMEM;
debugf3("%s(): init mci\n", __func__);
mci->pdev = pdev;
mci->dev = &pdev->dev;
mci->mtype_cap = MEM_FLAG_DDR;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
......@@ -160,12 +166,12 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
/* adjust FLAGS */
mci->mod_name = EDAC_MOD_STR;
mci->mod_ver = "$Revision: 1.1.2.6 $";
mci->mod_ver = I82860_REVISION;
mci->ctl_name = i82860_devs[dev_idx].ctl_name;
mci->edac_check = i82860_check;
mci->ctl_page_to_phys = NULL;
pci_read_config_word(mci->pdev, I82860_MCHCFG, &mchcfg_ddim);
pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
mchcfg_ddim = mchcfg_ddim & 0x180;
/*
......@@ -179,7 +185,7 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
u32 cumul_size;
struct csrow_info *csrow = &mci->csrows[index];
pci_read_config_word(mci->pdev, I82860_GBA + index * 2,
pci_read_config_word(pdev, I82860_GBA + index * 2,
&value);
cumul_size = (value & I82860_GBA_MASK) <<
......@@ -240,7 +246,7 @@ static void __devexit i82860_remove_one(struct pci_dev *pdev)
debugf0("%s()\n", __func__);
if ((mci = edac_mc_del_mc(pdev)) == NULL)
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
return;
edac_mc_free(mci);
......
......@@ -21,6 +21,8 @@
#include <linux/slab.h>
#include "edac_mc.h"
#define I82875P_REVISION " Ver: 2.0.0 " __DATE__
#define i82875p_printk(level, fmt, arg...) \
edac_printk(level, "i82875p", fmt, ##arg)
......@@ -185,18 +187,22 @@ static int i82875p_registered = 1;
static void i82875p_get_error_info(struct mem_ctl_info *mci,
struct i82875p_error_info *info)
{
struct pci_dev *pdev;
pdev = to_pci_dev(mci->dev);
/*
* This is a mess because there is no atomic way to read all the
* registers at once and the registers can transition from CE being
* overwritten by UE.
*/
pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts);
pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
pci_read_config_byte(mci->pdev, I82875P_DERRSYN, &info->derrsyn);
pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts2);
pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
pci_read_config_byte(pdev, I82875P_DES, &info->des);
pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
/*
* If the error is the same then we can for both reads then
......@@ -208,9 +214,9 @@ static void i82875p_get_error_info(struct mem_ctl_info *mci,
return;
if ((info->errsts ^ info->errsts2) & 0x0081) {
pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
pci_read_config_byte(mci->pdev, I82875P_DERRSYN,
pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
pci_read_config_byte(pdev, I82875P_DES, &info->des);
pci_read_config_byte(pdev, I82875P_DERRSYN,
&info->derrsyn);
}
}
......@@ -337,14 +343,14 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
}
debugf3("%s(): init mci\n", __func__);
mci->pdev = pdev;
mci->dev = &pdev->dev;
mci->mtype_cap = MEM_FLAG_DDR;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
mci->edac_cap = EDAC_FLAG_UNKNOWN;
/* adjust FLAGS */
mci->mod_name = EDAC_MOD_STR;
mci->mod_ver = "$Revision: 1.5.2.11 $";
mci->mod_ver = I82875P_REVISION;
mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
mci->edac_check = i82875p_check;
mci->ctl_page_to_phys = NULL;
......@@ -437,7 +443,7 @@ static void __devexit i82875p_remove_one(struct pci_dev *pdev)
debugf0("%s()\n", __func__);
if ((mci = edac_mc_del_mc(pdev)) == NULL)
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
return;
pvt = (struct i82875p_pvt *) mci->pvt_info;
......
......@@ -23,6 +23,8 @@
#include <linux/slab.h>
#include "edac_mc.h"
#define R82600_REVISION " Ver: 2.0.0 " __DATE__
#define r82600_printk(level, fmt, arg...) \
edac_printk(level, "r82600", fmt, ##arg)
......@@ -134,17 +136,20 @@ static unsigned int disable_hardware_scrub = 0;
static void r82600_get_error_info (struct mem_ctl_info *mci,
struct r82600_error_info *info)
{
pci_read_config_dword(mci->pdev, R82600_EAP, &info->eapr);
struct pci_dev *pdev;
pdev = to_pci_dev(mci->dev);
pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
if (info->eapr & BIT(0))
/* Clear error to allow next error to be reported [p.62] */
pci_write_bits32(mci->pdev, R82600_EAP,
pci_write_bits32(pdev, R82600_EAP,
((u32) BIT(0) & (u32) BIT(1)),
((u32) BIT(0) & (u32) BIT(1)));
if (info->eapr & BIT(1))
/* Clear error to allow next error to be reported [p.62] */
pci_write_bits32(mci->pdev, R82600_EAP,
pci_write_bits32(pdev, R82600_EAP,
((u32) BIT(0) & (u32) BIT(1)),
((u32) BIT(0) & (u32) BIT(1)));
}
......@@ -232,7 +237,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
}
debugf0("%s(): mci = %p\n", __func__, mci);
mci->pdev = pdev;
mci->dev = &pdev->dev;
mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
/* FIXME try to work out if the chip leads have been used for COM2
......@@ -253,7 +258,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
mci->edac_cap = EDAC_FLAG_NONE;
mci->mod_name = EDAC_MOD_STR;
mci->mod_ver = "$Revision: 1.1.2.6 $";
mci->mod_ver = R82600_REVISION;
mci->ctl_name = "R82600";
mci->edac_check = r82600_check;
mci->ctl_page_to_phys = NULL;
......@@ -265,7 +270,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
u32 row_base;
/* find the DRAM Chip Select Base address and mask */
pci_read_config_byte(mci->pdev, R82600_DRBA + index, &drbar);
pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
debugf1("MC%d: %s() Row=%d DRBA = %#0x\n", mci->mc_idx,
__func__, index, drbar);
......@@ -309,7 +314,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
if (disable_hardware_scrub) {
debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
__func__);
pci_write_bits32(mci->pdev, R82600_EAP, BIT(31), BIT(31));
pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
}
debugf3("%s(): success\n", __func__);
......@@ -338,7 +343,7 @@ static void __devexit r82600_remove_one(struct pci_dev *pdev)
debugf0("%s()\n", __func__);
if ((mci = edac_mc_del_mc(pdev)) == NULL)
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
return;
edac_mc_free(mci);
......
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