arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation

Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a,
no functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-29-broonie@kernel.orgSigned-off-by: Will Deacon <will@kernel.org>

arch/arm64/include/asm/sysreg.h

@@ -192,7 +192,6 @@
 
 #define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
 #define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
-#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)
 
 #define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
 #define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
@@ -737,28 +736,6 @@
 #define ID_AA64PFR1_MTE			0x2
 #define ID_AA64PFR1_MTE_ASYMM		0x3
 
-/* id_aa64zfr0 */
-#define ID_AA64ZFR0_EL1_F64MM_SHIFT	56
-#define ID_AA64ZFR0_EL1_F32MM_SHIFT	52
-#define ID_AA64ZFR0_EL1_I8MM_SHIFT	44
-#define ID_AA64ZFR0_EL1_SM4_SHIFT	40
-#define ID_AA64ZFR0_EL1_SHA3_SHIFT	32
-#define ID_AA64ZFR0_EL1_BF16_SHIFT	20
-#define ID_AA64ZFR0_EL1_BitPerm_SHIFT	16
-#define ID_AA64ZFR0_EL1_AES_SHIFT	4
-#define ID_AA64ZFR0_EL1_SVEver_SHIFT	0
-
-#define ID_AA64ZFR0_EL1_F64MM_IMP	0x1
-#define ID_AA64ZFR0_EL1_F32MM_IMP	0x1
-#define ID_AA64ZFR0_EL1_I8MM_IMP	0x1
-#define ID_AA64ZFR0_EL1_BF16_IMP	0x1
-#define ID_AA64ZFR0_EL1_SM4_IMP		0x1
-#define ID_AA64ZFR0_EL1_SHA3_IMP	0x1
-#define ID_AA64ZFR0_EL1_BitPerm_IMP	0x1
-#define ID_AA64ZFR0_EL1_AES_IMP		0x1
-#define ID_AA64ZFR0_EL1_AES_PMULL128	0x2
-#define ID_AA64ZFR0_EL1_SVEver_SVE2	0x1
-
 /* id_aa64mmfr0 */
 #define ID_AA64MMFR0_ECV_SHIFT		60
 #define ID_AA64MMFR0_FGT_SHIFT		56

arch/arm64/tools/sysreg

@@ -46,6 +46,52 @@
 # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
 # item ACCDATA) though it may be more taseful to do something else.
 
+Sysreg	ID_AA64ZFR0_EL1	3	0	0	4	4
+Res0	63:60
+Enum	59:56	F64MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	55:52	F32MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	51:48
+Enum	47:44	I8MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	43:40	SM4
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	39:36
+Enum	35:32	SHA3
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	31:24
+Enum	23:20	BF16
+	0b0000	NI
+	0b0001	IMP
+	0b0010	EBF16
+EndEnum
+Enum	19:16	BitPerm
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	15:8
+Enum	7:4	AES
+	0b0000	NI
+	0b0001	IMP
+	0b0010	PMULL128
+EndEnum
+Enum	3:0	SVEver
+	0b0000	IMP
+	0b0001	SVE2
+EndEnum
+EndSysreg
+
 Sysreg	ID_AA64SMFR0_EL1	3	0	0	4	5
 Enum	63	FA64
 	0b0	NI